VPSLLD

VPSLLD shifts each doubleword left by one shared count, filling with zeros: the VEX and EVEX form of PSLLD, whose page covers the operation, with the count rules PSLLW gives for the family. Even in the YMM and ZMM forms the count is an immediate or the low quadword of an XMM register or of memory, and any count above 31 clears the element. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms (AVX-512F) add masking, the 512-bit width and, in the immediate form only, a source read from memory, whole or as one broadcast doubleword. Every form writes a separate destination, zeroes it above the vector length and takes memory at any alignment.

On Zen 5, the recorded vpslld ymm0, ymm13, 0x10 shifted all eight doublewords alike, 7FFFFFFFh becoming FFFF0000h in either 128-bit lane; vpslld ymm7, ymm11, xmm7, with a count of 33, cleared all eight; and vpslld zmm9{k5}, dword bcst [mem], 3 wrote 0, from 80000000h, into the nine elements k5 selects and kept the other seven.

In compiled code#

In our builds at -O2 over uint32_t arrays, b[i] << 3 is VPSLLD by 3 with -march=x86-64-v3 in GCC 14 and Clang 23; with -march=x86-64-v4 both shift straight from memory, which only EVEX can. For b[i] << n, GCC moves n into an XMM register for VPSLLD, while Clang broadcasts it for VPSLLVD. A rotate by 7 is VPSLLD, VPSRLD and VPOR at -v3, one VPROLD at -v4. c[i] ? b[i] << 3 : b[i] shifts and blends at -v3; at -v4 both mask the shift itself.

Intel’s optimization manual compares masking with blending on a VPSLLD and a VPSRLD: merge-masked into one register, they wait for each other, and computing both and merging once was faster (Section 17.2.3; see the guide). AMD’s latency spreadsheet for Zen 5 gives the EVEX immediate form one cycle on pipes FP2 and FP3 and the count from a register two cycles on FP0 and FP1, the figure its single row for the VEX forms gives them all.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

count = src3.q[0]
for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.d[i]
        if count < 32:
            zmm1.d[i] = a << count
        else:
            zmm1.d[i] = 0
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = src2.d[i]
        if imm8 < 32:
            zmm1.d[i] = a << imm8
        else:
            zmm1.d[i] = 0
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VPSLLD xmm, xmm, xmm/m128 VPSLLD xmm, xmm, imm8 VPSLLD ymm, ymm, imm8

avx-type-7

VPSLLD ymm, ymm, xmm/m128

avx-type-4

VPSLLD xmm {k}{z}, xmm, xmm/m128 VPSLLD ymm {k}{z}, ymm, xmm/m128 VPSLLD zmm {k}{z}, zmm, xmm/m128

AVX512-E4NF

VPSLLD xmm {k}{z}, xmm/m128/m32bcst, imm8 VPSLLD ymm {k}{z}, ymm/m256/m32bcst, imm8 VPSLLD zmm {k}{z}, zmm/m512/m32bcst, imm8

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

VPSLLD xmm {k}{z}, m128/m32bcst, imm8 VPSLLD ymm {k}{z}, m256/m32bcst, imm8 VPSLLD zmm {k}{z}, m512/m32bcst, imm8

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSLLD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLDQ
• VPSLLQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ

All 253 AVX instructions

More AVX2 instructions

• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSCATTERDQ
• VPSCATTERQD
• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB

All 686 AVX10.1 instructions