x86-64.net

Instruction

VPSLLDQ

Shifts each 128-bit lane left by a number of bytes given by an immediate.

Extensions
Forms
8 (2 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPSLLDQ shifts bytes left by an immediate count, filling with zeros: the VEX and EVEX form of PSLLDQ, whose page covers the byte shift and its mix-up with VPSLLQ. The new forms write a separate destination and clear it above the vector length; VEX.128 needs AVX, VEX.256 AVX2, and the EVEX forms AVX512BW (with AVX512VL below 512 bits, or AVX10.1). EVEX adds the 512-bit width and a source read from memory at any alignment, but no write mask and no broadcast.

Each lane on its own

The wider forms do not shift the whole register: each 128-bit lane shifts by the same count, and bytes never cross into the next lane. On Zen 5, the recorded vpslldq ymm8, ymm15, 0x1 put zero in byte 16 as well as in byte 0, dropping byte 15 of the low lane instead of moving it up, and vpslldq zmm14, zmmword ptr [mem], 0x8 moved the low 8 bytes of each of the four lanes to its high half. A count above 15 clears the lane, and vpslldq xmm7, xmm12, 0xf left only the old byte 0 in byte 15.

In compiled code

_mm256_bslli_epi128 and _mm512_bslli_epi128 say so in their names; _mm256_slli_si256 is the older name of the same per-lane shift. In our builds at -O2, GCC 14 and Clang 23 compile two of them by 4 and 8 bytes, each followed by a VPADDD, to two VPSLLDQ, the prefix sum PSLLDQ’s page describes, but on a ymm register it adds up four elements within each lane, not eight. Neither vectorizes a plain C running sum, a[i] += a[i-1], over a fixed-size int32_t array. With -march=x86-64-v4 both take the source of _mm256_bslli_epi128 straight from memory, which only EVEX allows, and a 16-byte vector shuffle that moves bytes up by 3 and pulls in zeros becomes vpslldq xmm0, xmm0, 0x3.

AMD’s latency spreadsheet for Zen 5 gives the VEX row and the EVEX row the same figures: one macro-op on pipes FP1 and FP2, a latency of 2 cycles and two per cycle. VPSRLDQ shifts the other way.

Forms

Every encoding of VPSLLDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSLLDQ xmm, xmm, imm8 VPSLLDQ_XMMdq_XMMdq_IMMbVEX.128.66.0F.WIG 73 /7 ibAVX
VPSLLDQ ymm, ymm, imm8 VPSLLDQ_YMMqq_YMMqq_IMMbVEX.256.66.0F.WIG 73 /7 ibAVX2
VPSLLDQ xmm, xmm, imm8 VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512EVEX.128.66.0F.WIG 73 /7 ibAVX10.1 or AVX512BW + AVX512VL
VPSLLDQ xmm, m128, imm8 VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512EVEX.128.66.0F.WIG 73 /7 ibAVX10.1 or AVX512BW + AVX512VL
VPSLLDQ ymm, ymm, imm8 VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512EVEX.256.66.0F.WIG 73 /7 ibAVX10.1 or AVX512BW + AVX512VL
VPSLLDQ ymm, m256, imm8 VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512EVEX.256.66.0F.WIG 73 /7 ibAVX10.1 or AVX512BW + AVX512VL
VPSLLDQ zmm, zmm, imm8 VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512EVEX.512.66.0F.WIG 73 /7 ibAVX10.1 or AVX512BW
VPSLLDQ zmm, m512, imm8 VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512EVEX.512.66.0F.WIG 73 /7 ibAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, imm8
ymm, ymm, imm8		ymm, ymm, imm8xmm, xmm, imm8xmm, m128, imm8ymm, m256, imm8zmm, zmm, imm8zmm, m512, imm8
Sandy Bridge1 / 0.5p15
Haswell, Broadwell, Skylake1 / 1p51 / 1p5
Skylake-SP1 / 1p51 / 1p51 / 1p57 / 1p58 / 1p51 / 1p58 / 1p5
Ice Lake1 / 0.5p151 / 0.5p151 / 0.5p157 / 0.5p158 / 0.5p151 / 1p58 / 1p5
Alder Lake1 / 0.5p151 / 0.5p15
Sapphire Rapids1 / 0.5p151 / 0.5p151 / 0.5p158 / 0.5p159 / 0.5p151 / 1p59 / 1p5
Lunar Lake1 / 0.5V2 V31 / 0.5V2 V3
Piledriver2 / 1FPU1 FPXBR
Zen1 / 0.5FPU1 FPU21 / 1FPU1 FPU2
Zen 21 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 31 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 42 / 11FP0 FP12 / 12FP0 FP11 / 0.5FP1 FP28 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP0 FP18 / 1FP1 FP2
Jaguar1 / 0.5FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model, xmm form: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2912; AMD 58455, row 1170).
  2. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2913; AMD 58455, row 1170).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Byte shift: the bytes move up by imm8 places within each 128-bit lane, and zeros come in.
VPSLLDQ with imm8 = 3With imm8 = 3, result bytes 15 to 0: a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0, 0, 0, 0.0123456789101112131415xmm2or m128a000a0a1a2a3a4a5a6a7a8a9a10a11a12xmm1

Example: imm8 = 3. The ymm and zmm forms repeat this in each 128-bit lane.

With imm8 = 3, result bytes 15 to 0: a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0, 0, 0, 0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if i % 16 >= imm8:
        zmm1.b[i] = src2.b[i - imm8]
    else:
        zmm1.b[i] = 0
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPSLLDQ xmm, xmm/m128, imm8 VPSLLDQ ymm, ymm/m256, imm8 VPSLLDQ zmm, zmm/m512, imm8
xmm, ymm, zmmexplicitwrite
xmm/m128, ymm/m256, zmm/m512explicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-7
EVEX forms
AVX512-E4NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSLLDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_bslli_si128 __m128i _mm_bslli_si128(__m128i a, const int imm)

VPSLLDQ xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_slli_si128 __m128i _mm_slli_si128(__m128i a, const int imm)

VPSLLDQ xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm256_bslli_epi128 __m256i _mm256_bslli_epi128(__m256i a, const int imm)

VPSLLDQ ymm, ymm, imm8 VEX.256 -mavx2

_mm256_slli_si256 __m256i _mm256_slli_si256(__m256i a, const int imm)

VPSLLDQ ymm, ymm, imm8 VEX.256 -mavx2

_mm512_bslli_epi128 __m512i _mm512_bslli_epi128(__m512i a, const int imm)

VPSLLDQ zmm, zmm, imm8 EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-441 (PSLLDQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.