VPSLLQ

VPSLLQ shifts each quadword left by one shared count, filling with zeros: the VEX and EVEX form of PSLLQ, whose page covers the operation and why bits never cross from one quadword to the next. The forms are those of VPSLLD: three operands, VEX.128 for AVX and VEX.256 for AVX2, EVEX (AVX-512F) with masking, the 512-bit width and a memory source for the immediate form, here whole or as one broadcast quadword. The count is an immediate or the low quadword of an XMM register or of memory, and anything above 63 clears the element.

Zen 5’s recorded cases: vpsllq ymm1, ymm2, xmm3 took its count, 3, from the low quadword of XMM3 and ignored the random bits above it, turning FFFFFFFFFFFFFFFFh into FFFFFFFFFFFFFFF8h in both lanes; {evex} vpsllq ymm9, ymm9, [mem], whose count was 8000000000000000h, cleared all four quadwords; and vpsllq zmm0{k5}, qword bcst [mem], 0xff cleared the four elements k5 selects and kept the other four.

In compiled code#

In our builds at -O2 over uint64_t arrays, b[i] << 3 is VPSLLQ by 3 with -march=x86-64-v3 in GCC 14 and Clang 23, read straight from memory with -march=x86-64-v4. AVX2 has no 64-bit multiply, and b[i] * c[i] at -v3 is built from 32-bit products in both compilers: two VPSRLQ by 32 bring the high halves down, three VPMULUDQ form the partial products, and VPSLLQ by 32 moves the sum of the cross products up before the last VPADDQ. At -v4 it is one VPMULLQ, from AVX512DQ.

Intel’s optimization manual names VPSLLQ with VPMULUDQ, VPADDQ, VPSRLQ, VPBROADCASTQ and VPERMQ as the AVX2 instructions for vectorized modular multiplication, with numbers held as 29-bit digits in doublewords so that the 64-bit products leave room for carries (Section 15.16.2). AMD’s latency spreadsheet for Zen 5 gives the EVEX immediate form one cycle on pipes FP2 and FP3 and the count from a register two cycles on FP0 and FP1, the figure its one row for the VEX forms gives them all.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

count = src3.q[0]
for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm2.q[i]
        if count < 64:
            zmm1.q[i] = a << count
        else:
            zmm1.q[i] = 0
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = src2.q[i]
        if imm8 < 64:
            zmm1.q[i] = a << imm8
        else:
            zmm1.q[i] = 0
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VPSLLQ xmm, xmm, xmm/m128 VPSLLQ xmm, xmm, imm8 VPSLLQ ymm, ymm, imm8

avx-type-7

VPSLLQ ymm, ymm, xmm/m128

avx-type-4

VPSLLQ xmm {k}{z}, xmm, xmm/m128 VPSLLQ ymm {k}{z}, ymm, xmm/m128 VPSLLQ zmm {k}{z}, zmm, xmm/m128

AVX512-E4NF

VPSLLQ xmm {k}{z}, xmm/m128/m64bcst, imm8 VPSLLQ ymm {k}{z}, ymm/m256/m64bcst, imm8 VPSLLQ zmm {k}{z}, zmm/m512/m64bcst, imm8

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

VPSLLQ xmm {k}{z}, m128/m64bcst, imm8 VPSLLQ ymm {k}{z}, m256/m64bcst, imm8 VPSLLQ zmm {k}{z}, m512/m64bcst, imm8

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSLLQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD

All 253 AVX instructions

More AVX2 instructions

• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSCATTERQQ
• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ

All 686 AVX10.1 instructions