VPSLLVD

VPSLLVD shifts each doubleword left by its own count, taken from the matching element of the second source, and fills with zeros from the right. VPSLLD shifts every element by one count, from an immediate or the low quadword of an XMM register. AVX2 introduced the variable shifts in three directions, VPSLLVD, VPSRLVD and VPSRAVD, each for doublewords and quadwords (VPSLLVQ); AVX-512 added masking, a broadcast count and the 512-bit form, and AVX512BW the word form VPSLLVW.

Counts of 32 and more#

Each count is the whole unsigned doubleword. From 32 up the element becomes zero, as the page’s pseudocode says; the count is not masked to 5 bits as SHL masks it. The cases recorded on Zen 5 show zero for counts 32, 33, 63, 80000000h and FFFFFFFFh. C leaves x << n undefined for n of 32 and more, so GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 compile a[i] = b[i] << c[i] over a fixed-size uint32_t array to VPSLLVD alone, and 1u << c[i] to VPSLLVD of a vector of ones.

Clang also relies on the zero. For a rotate by a variable count, (x << (n & 31)) | (x >> (-n & 31)), it shifts right by 32 - (n & 31) with VPSRLVD; when n & 31 is 0 that count is 32, which gives 0 and leaves x intact. GCC computes -n & 31 instead. With AVX-512, Clang turns the whole rotate into one VPROLVD, while GCC keeps the shifts.

Without AVX2#

SSE has no variable shift. For the baseline or SSE4.1, GCC keeps the loop scalar with SAL, while Clang builds 2 to the power of each count as a float: it shifts the count into the exponent field with PSLLD by 23, adds the bits of 1.0, converts with CVTTPS2DQ, and multiplies, with PMULLD under SSE4.1 or two PMULUDQs under SSE2.

AMD’s Zen 5 guide lists VPSLLVD as one macro-op with a latency of one cycle. Intel’s guide puts the variable shifts in the same execution units of Golden Cove as the shifts by an immediate count, two for 256-bit vectors and one for 512-bit ones (Table 2-4).

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.d[i]
        b = src3.d[i]
        zmm1.d[i] = a << b if b < 32 else 0
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSLLVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSHLDD
• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB

All 686 AVX10.1 instructions