x86-64.net

Instruction

VPSLLVQ

Shifts each quadword left by the count in the matching element of the second source.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPSLLVQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSLLVQ xmm, xmm, m128 VPSLLVQ_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.W1 47 /rAVX2
VPSLLVQ xmm, xmm, xmm VPSLLVQ_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.W1 47 /rAVX2
VPSLLVQ ymm, ymm, m256 VPSLLVQ_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.W1 47 /rAVX2
VPSLLVQ ymm, ymm, ymm VPSLLVQ_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.W1 47 /rAVX2
VPSLLVQ zmm {k}{z}, zmm, zmm VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512EVEX.512.66.0F38.W1 47 /rAVX10.1 or AVX512F
VPSLLVQ zmm {k}{z}, zmm, m512/m64bcst VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512EVEX.512.66.0F38.W1 47 /rAVX10.1 or AVX512F
VPSLLVQ xmm {k}{z}, xmm, xmm VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512EVEX.128.66.0F38.W1 47 /rAVX10.1 or AVX512F + AVX512VL
VPSLLVQ xmm {k}{z}, xmm, m128/m64bcst VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512EVEX.128.66.0F38.W1 47 /rAVX10.1 or AVX512F + AVX512VL
VPSLLVQ ymm {k}{z}, ymm, ymm VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512EVEX.256.66.0F38.W1 47 /rAVX10.1 or AVX512F + AVX512VL
VPSLLVQ ymm {k}{z}, ymm, m256/m64bcst VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512EVEX.256.66.0F38.W1 47 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSLLVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_sllv_epi64 __m128i _mm_sllv_epi64(__m128i __X, __m128i __Y)

VPSLLVQ xmm, xmm, xmm VEX.128 -mavx2

_mm_mask_sllv_epi64 __m128i _mm_mask_sllv_epi64(__m128i __W, __mmask8 __U, __m128i __X, __m128i __Y)

VPSLLVQ xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_sllv_epi64 __m128i _mm_maskz_sllv_epi64(__mmask8 __U, __m128i __X, __m128i __Y)

VPSLLVQ xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm256_sllv_epi64 __m256i _mm256_sllv_epi64(__m256i __X, __m256i __Y)

VPSLLVQ ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_sllv_epi64 __m256i _mm256_mask_sllv_epi64(__m256i __W, __mmask8 __U, __m256i __X, __m256i __Y)

VPSLLVQ ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_sllv_epi64 __m256i _mm256_maskz_sllv_epi64(__mmask8 __U, __m256i __X, __m256i __Y)

VPSLLVQ ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm512_sllv_epi64 __m512i _mm512_sllv_epi64(__m512i __X, __m512i __Y)

VPSLLVQ zmm, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_sllv_epi64 __m512i _mm512_mask_sllv_epi64(__m512i __W, __mmask8 __U, __m512i __X, __m512i __Y)

VPSLLVQ zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_sllv_epi64 __m512i _mm512_maskz_sllv_epi64(__mmask8 __U, __m512i __X, __m512i __Y)

VPSLLVQ zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.