VPSLLVQ

VPSLLVQ shifts each quadword left by its own count, taken from the matching quadword of the second source, and fills with zeros from the right. It is the 64-bit member of the variable shifts that AVX2 introduced; VPSLLVD and VPSRLVQ describe the family, the counts read as whole unsigned elements, and what compilers do without AVX2. Every count from 64 up gives zero: the cases recorded on Zen 5 show zero for counts 40h, 41h, 7Fh, 8000000000000000h and FFFFFFFFFFFFFFFFh, while 3Fh turned an all-ones quadword into 8000000000000000h. With a write mask and a broadcast count, vpsllvq zmm7{k3}, zmm12, qword bcst [mem] applied a count of 8000000000000000h to the six elements K3 selects, zeroing them, and kept the other two.

One bit per element#

Setting bit n of a 64-bit word, d[i] = 1ull << (x[i] & 63), is how code builds masks for bitsets and bitboards. Clang 23 at -O2 with -march=x86-64-v3 vectorizes it as a VPAND of the indices with 63 and VPSLLVQ of a vector of ones, four per instruction; with 32-bit indices it widens them first with VPMOVZXDQ. GCC 14 keeps the loop scalar with SHLX, and drops the AND, since SHLX masks its count to six bits itself. VPSLLVQ does not, so in vector code the AND stays.

The plain a[i] = b[i] << c[i] over uint64_t arrays is one VPSLLVQ per vector in both compilers, with the counts read from memory in Clang. GCC 14 first ANDs every count with a broadcast FFFFFFFFh, which changes no count below 64, the only ones C defines; with -march=x86-64-v4 it does the same on ZMM registers.

The arithmetic right shift of quadwords, VPSRAVQ, came only with AVX-512. AMD’s latency spreadsheet for Zen 5 lists VPSLLVQ, VEX or EVEX, as one macro-op with a latency of one cycle on the pipes FP2 and FP3.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm2.q[i]
        b = src3.q[i]
        zmm1.q[i] = a << b if b < 64 else 0
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSLLVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSHLDQ
• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW

All 686 AVX10.1 instructions