VPSLLVW

VPSLLVW shifts each word left by its own count, taken from the matching word of the second source, and fills with zeros from the right. It is the word form that AVX512BW added to AVX2’s variable shifts, which VPSLLVD describes: each count is the whole unsigned element, and every count from 16 up gives zero. VPSRLVW shifts right and VPSRAVW right with the sign; VPSLLW shifts every word by one count. It has no broadcast form.

Recorded on Zen 5#

• Counts to 15. In vpsllvw xmm1, xmm2, xmm3, 7FFFh shifted by 1 gave FFFEh, 000Fh by 8 gave 0F00h, and 8000h by 15 gave 0.
• Counts from 16. 8000h by 16, 7FFFh by 17 and the counts 8000h and FFFFh all gave 0; the count is not reduced modulo 16.
• Merging into the count register. In vpsllvw zmm7{k6}, zmm12, zmm7 the counts came from ZMM7 itself and the words K6 left out kept their old counts.

In compiled code#

For o[i] = a[i] << (b[i] & 15) over uint16_t arrays, Clang 23 at -O2 with -march=x86-64-v4 masks the counts and shifts with VPSLLVW on YMM registers. GCC 14 widens both operands to doublewords with VPMOVZXWD, shifts them with VPSLLVD and joins the low words with VPERMT2W, the code it uses for the same loop with -march=x86-64-v3, where it packs with VPACKUSDW instead. For the right shift of the same operands GCC does use VPSRLVW.

AMD’s Zen 5 latency spreadsheet gives VPSLLVW one cycle and two per cycle on pipes FP2 and FP3, as VPSLLVD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.w[i]
        b = src3.w[i]
        zmm1.w[i] = a << b if b < 16 else 0
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSLLVW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSHLDVD
• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB

All 686 AVX10.1 instructions