VPSLLW

VPSLLW is the VEX and EVEX form of PSLLW, whose page covers the shift and its count: one for every word, from an immediate or the low quadword of an XMM register or of memory, and anything above 15 clears the word. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1, not AVX-512F, and add masking, the 512-bit width and, in the immediate form only, a source read from memory, though never a broadcast one.

On Zen 5, {evex} vpsllw ymm24, ymm3, xmmword ptr [mem] took its count, 1, from the low quadword and ignored the random one above it, turning 7FFFh into FFFEh in both lanes; vpsllw ymm0, ymm13, xmm9, with a count of 100000001h, cleared all sixteen words; and vpsllw zmm9{k7}, zmm9, xmmword ptr [mem], whose count was 8000000000000000h, cleared the words K7 selects and kept the rest.

In compiled code#

In our builds at -O2 over uint16_t arrays, b[i] << 3 is VPSLLW by 3 with -march=x86-64-v3 in GCC 14 and Clang 23; with -march=x86-64-v4 both shift straight from memory, which only EVEX can, GCC in zmm and Clang in ymm registers. c[i] ? b[i] << 3 : b[i] shifts and blends with VPBLENDVB at -v3; at -v4 GCC masks the shift itself, while Clang merges afterwards with a masked VMOVDQU16.

AMD’s latency spreadsheet for Zen 5 gives the EVEX immediate form one cycle on pipes FP2 and FP3 and the count from a register two cycles on FP0 and FP1, the figure its one row for the VEX forms gives them all.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

count = src3.q[0]
for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        a = zmm2.w[i]
        if count < 16:
            zmm1.w[i] = a << count
        else:
            zmm1.w[i] = 0
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        a = src2.w[i]
        if imm8 < 16:
            zmm1.w[i] = a << imm8
        else:
            zmm1.w[i] = 0
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VPSLLW xmm, xmm, xmm/m128 VPSLLW xmm, xmm, imm8 VPSLLW ymm, ymm, imm8

avx-type-7

VPSLLW ymm, ymm, xmm/m128

avx-type-4

VPSLLW xmm {k}{z}, xmm/m128, imm8 VPSLLW ymm {k}{z}, ymm/m256, imm8 VPSLLW zmm {k}{z}, zmm/m512, imm8

AVX512-E4

VPSLLW xmm {k}{z}, xmm, xmm/m128 VPSLLW ymm {k}{z}, ymm, xmm/m128 VPSLLW zmm {k}{z}, zmm, xmm/m128

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

VPSLLW xmm {k}{z}, m128, imm8 VPSLLW ymm {k}{z}, m256, imm8 VPSLLW zmm {k}{z}, m512, imm8

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSLLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW

All 253 AVX instructions

More AVX2 instructions

• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSHLDVQ
• VPSHLDVW
• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW

All 686 AVX10.1 instructions