x86-64.net

Instruction

VPSRAD

Shifts doublewords right arithmetically by one count from a register or an immediate.

Extensions
Forms
18 (6 VEX, 12 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPSRAD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSRAD xmm, xmm, m128 VPSRAD_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG E2 /rAVX
VPSRAD xmm, xmm, xmm VPSRAD_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG E2 /rAVX
VPSRAD xmm, xmm, imm8 VPSRAD_XMMdq_XMMdq_IMMbVEX.128.66.0F.WIG 72 /4 ibAVX
VPSRAD ymm, ymm, m128 VPSRAD_YMMqq_YMMqq_MEMdqVEX.256.66.0F.WIG E2 /rAVX2
VPSRAD ymm, ymm, xmm VPSRAD_YMMqq_YMMqq_XMMqVEX.256.66.0F.WIG E2 /rAVX2
VPSRAD ymm, ymm, imm8 VPSRAD_YMMqq_YMMqq_IMMbVEX.256.66.0F.WIG 72 /4 ibAVX2
VPSRAD zmm {k}{z}, zmm, xmm VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512EVEX.512.66.0F.W0 E2 /rAVX10.1 or AVX512F
VPSRAD zmm {k}{z}, zmm, m128 VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512EVEX.512.66.0F.W0 E2 /rAVX10.1 or AVX512F
VPSRAD zmm {k}{z}, zmm, imm8 VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512EVEX.512.66.0F.W0 72 /4 ibAVX10.1 or AVX512F
VPSRAD zmm {k}{z}, m512/m32bcst, imm8 VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.512.66.0F.W0 72 /4 ibAVX10.1 or AVX512F
VPSRAD xmm {k}{z}, xmm, imm8 VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512EVEX.128.66.0F.W0 72 /4 ibAVX10.1 or AVX512F + AVX512VL
VPSRAD xmm {k}{z}, m128/m32bcst, imm8 VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.128.66.0F.W0 72 /4 ibAVX10.1 or AVX512F + AVX512VL
VPSRAD xmm {k}{z}, xmm, xmm VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512EVEX.128.66.0F.W0 E2 /rAVX10.1 or AVX512F + AVX512VL
VPSRAD xmm {k}{z}, xmm, m128 VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512EVEX.128.66.0F.W0 E2 /rAVX10.1 or AVX512F + AVX512VL
VPSRAD ymm {k}{z}, ymm, imm8 VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512EVEX.256.66.0F.W0 72 /4 ibAVX10.1 or AVX512F + AVX512VL
VPSRAD ymm {k}{z}, m256/m32bcst, imm8 VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.256.66.0F.W0 72 /4 ibAVX10.1 or AVX512F + AVX512VL
VPSRAD ymm {k}{z}, ymm, xmm VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512EVEX.256.66.0F.W0 E2 /rAVX10.1 or AVX512F + AVX512VL
VPSRAD ymm {k}{z}, ymm, m128 VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512EVEX.256.66.0F.W0 E2 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRAD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_sra_epi32 __m128i _mm_sra_epi32(__m128i __a, __m128i __count)

VPSRAD xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_srai_epi32 __m128i _mm_srai_epi32(__m128i __a, int __count)

VPSRAD xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled; with __count a constant

_mm_mask_sra_epi32 __m128i _mm_mask_sra_epi32(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPSRAD xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_srai_epi32 __m128i _mm_mask_srai_epi32(__m128i __W, __mmask8 __U, __m128i __A, unsigned int __B)

VPSRAD xmm {k}, xmm, imm8 EVEX.128 -mavx512vlwith __B a constant

_mm_maskz_sra_epi32 __m128i _mm_maskz_sra_epi32(__mmask8 __U, __m128i __A, __m128i __B)

VPSRAD xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_srai_epi32 __m128i _mm_maskz_srai_epi32(__mmask8 __U, __m128i __A, unsigned int __B)

VPSRAD xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vlwith __B a constant

_mm256_sra_epi32 __m256i _mm256_sra_epi32(__m256i __a, __m128i __count)

VPSRAD ymm, ymm, xmm VEX.256 -mavx2

_mm256_srai_epi32 __m256i _mm256_srai_epi32(__m256i __a, int __count)

VPSRAD ymm, ymm, imm8 VEX.256 -mavx2with __count a constant

_mm256_mask_sra_epi32 __m256i _mm256_mask_sra_epi32(__m256i __W, __mmask8 __U, __m256i __A, __m128i __B)

VPSRAD ymm {k}, ymm, xmm EVEX.256 -mavx512vl

_mm256_mask_srai_epi32 __m256i _mm256_mask_srai_epi32(__m256i __W, __mmask8 __U, __m256i __A, unsigned int __B)

VPSRAD ymm {k}, ymm, imm8 EVEX.256 -mavx512vlwith __B a constant

_mm256_maskz_sra_epi32 __m256i _mm256_maskz_sra_epi32(__mmask8 __U, __m256i __A, __m128i __B)

VPSRAD ymm {k}{z}, ymm, xmm EVEX.256 -mavx512vl

_mm256_maskz_srai_epi32 __m256i _mm256_maskz_srai_epi32(__mmask8 __U, __m256i __A, unsigned int __B)

VPSRAD ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vlwith __B a constant

_mm512_sra_epi32 __m512i _mm512_sra_epi32(__m512i __A, __m128i __B)

VPSRAD zmm, zmm, xmm EVEX.512 -mavx512f

_mm512_srai_epi32 __m512i _mm512_srai_epi32(__m512i __A, unsigned int __B)

VPSRAD zmm, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

_mm512_mask_sra_epi32 __m512i _mm512_mask_sra_epi32(__m512i __W, __mmask16 __U, __m512i __A, __m128i __B)

VPSRAD zmm {k}, zmm, xmm EVEX.512 -mavx512f

_mm512_mask_srai_epi32 __m512i _mm512_mask_srai_epi32(__m512i __W, __mmask16 __U, __m512i __A, unsigned int __B)

VPSRAD zmm {k}, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

_mm512_maskz_sra_epi32 __m512i _mm512_maskz_sra_epi32(__mmask16 __U, __m512i __A, __m128i __B)

VPSRAD zmm {k}{z}, zmm, xmm EVEX.512 -mavx512f

_mm512_maskz_srai_epi32 __m512i _mm512_maskz_srai_epi32(__mmask16 __U, __m512i __A, unsigned int __B)

VPSRAD zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.