VPSRAQ

VPSRAQ shifts each quadword right by one shared count, copying its sign bit into the vacated bits. It works as VPSRAD does for doublewords, with the count as an immediate or in the low quadword of an XMM register or 16 bytes of memory, but it has no legacy or VEX form: SSE2 and AVX2 shift quadwords right only logically, and the VPSRAD page shows the three-instruction substitute that -march=x86-64-v3 code needs. VPSRAQ came with AVX-512F, with masking, a broadcast source in the immediate form and the 128- and 256-bit forms under AVX512VL. VPSRAVQ takes a count per element.

Recorded on Zen 5#

• Large counts fill with the sign. With 40h in XMM29, vpsraq zmm14{k5}, zmm8, xmm29 turned 1 and 7FFFFFFFFFFFFFFFh into 0 and 8000000000000000h into all ones.
• The whole quadword is the count. {evex} vpsraq ymm0, ymm31, [mem] read 0000000100000001h, a count of 2^32 + 1, and filled every element with its sign rather than shifting by 1.
• Immediate. vpsraq zmm24{k3}, zmm3, 0x3 turned 8000000000000000h into F000000000000000h and 7FFFFFFFFFFFFFFFh into 0FFFFFFFFFFFFFFFh.

In compiled code#

With -march=x86-64-v4, GCC 14 and Clang 23 at -O2 compile a[i] >> 5 over int64_t arrays to VPSRAQ by 5, GCC on ZMM and Clang on YMM registers, and the sign mask a[i] >> 63 to VPSRAQ by 63. Sign extension of the low 24 bits, (int64_t)((uint64_t)a[i] << 40) >> 40, is VPSLLQ and VPSRAQ by 40 in both. They part on the rest:

• A count in a variable, the same for every element, is VPSRAQ with the count in an XMM register in GCC and VPSRAVQ with the count broadcast in Clang.
• Division by 4. Clang adds the bias 3 for negative values from VPSRAQ by 63 and VPSRLQ by 62, then shifts with VPSRAQ by 2. GCC marks the negative elements with VPCMPQ, puts 3 in them with a zero-masked move and adds that before the shift.
• Out-of-range immediates. _mm512_srai_epi64(x, 70) is VPSRAQ by 70 in GCC and by 63, the same result, in Clang.

AMD’s Zen 5 latency spreadsheet gives the immediate form one cycle on pipes FP2 and FP3 and the count from a register two cycles on FP0 and FP1, two per cycle each, as for VPSRAD. Zen 5’s 12 recorded cases cover the register, memory and immediate forms, broadcast included, at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

count = src3.q[0]
for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = zmm2.sq[i] >> count
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = src2.sq[i] >> imm8
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VPSRAQ xmm {k}{z}, xmm, xmm/m128 VPSRAQ ymm {k}{z}, ymm, xmm/m128 VPSRAQ zmm {k}{z}, zmm, xmm/m128

AVX512-E4NF

VPSRAQ xmm {k}{z}, xmm/m128/m64bcst, imm8 VPSRAQ ymm {k}{z}, ymm/m256/m64bcst, imm8 VPSRAQ zmm {k}{z}, zmm/m512/m64bcst, imm8

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

VPSRAQ xmm {k}{z}, m128/m64bcst, imm8 VPSRAQ ymm {k}{z}, m256/m64bcst, imm8 VPSRAQ zmm {k}{z}, m512/m64bcst, imm8

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRAQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSHLDW
• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD

All 686 AVX10.1 instructions