x86-64.net

Instruction

VPSRAQ

Shifts quadwords right arithmetically by one count from a register or an immediate.

Extensions
Forms
12 (12 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPSRAQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSRAQ zmm {k}{z}, zmm, xmm VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512EVEX.512.66.0F.W1 E2 /rAVX10.1 or AVX512F
VPSRAQ zmm {k}{z}, zmm, m128 VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512EVEX.512.66.0F.W1 E2 /rAVX10.1 or AVX512F
VPSRAQ zmm {k}{z}, zmm, imm8 VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512EVEX.512.66.0F.W1 72 /4 ibAVX10.1 or AVX512F
VPSRAQ zmm {k}{z}, m512/m64bcst, imm8 VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512EVEX.512.66.0F.W1 72 /4 ibAVX10.1 or AVX512F
VPSRAQ xmm {k}{z}, xmm, xmm VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512EVEX.128.66.0F.W1 E2 /rAVX10.1 or AVX512F + AVX512VL
VPSRAQ xmm {k}{z}, xmm, m128 VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512EVEX.128.66.0F.W1 E2 /rAVX10.1 or AVX512F + AVX512VL
VPSRAQ xmm {k}{z}, xmm, imm8 VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512EVEX.128.66.0F.W1 72 /4 ibAVX10.1 or AVX512F + AVX512VL
VPSRAQ xmm {k}{z}, m128/m64bcst, imm8 VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512EVEX.128.66.0F.W1 72 /4 ibAVX10.1 or AVX512F + AVX512VL
VPSRAQ ymm {k}{z}, ymm, xmm VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512EVEX.256.66.0F.W1 E2 /rAVX10.1 or AVX512F + AVX512VL
VPSRAQ ymm {k}{z}, ymm, m128 VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512EVEX.256.66.0F.W1 E2 /rAVX10.1 or AVX512F + AVX512VL
VPSRAQ ymm {k}{z}, ymm, imm8 VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512EVEX.256.66.0F.W1 72 /4 ibAVX10.1 or AVX512F + AVX512VL
VPSRAQ ymm {k}{z}, m256/m64bcst, imm8 VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512EVEX.256.66.0F.W1 72 /4 ibAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRAQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_sra_epi64 __m128i _mm_sra_epi64(__m128i __A, __m128i __B)

VPSRAQ xmm, xmm, xmm EVEX.128 -mavx512vl

_mm_srai_epi64 __m128i _mm_srai_epi64(__m128i __A, unsigned int __imm)

VPSRAQ xmm, xmm, imm8 EVEX.128 -mavx512vlwith __imm a constant

_mm_mask_sra_epi64 __m128i _mm_mask_sra_epi64(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPSRAQ xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_srai_epi64 __m128i _mm_mask_srai_epi64(__m128i __W, __mmask8 __U, __m128i __A, unsigned int __imm)

VPSRAQ xmm {k}, xmm, imm8 EVEX.128 -mavx512vlwith __imm a constant

_mm_maskz_sra_epi64 __m128i _mm_maskz_sra_epi64(__mmask8 __U, __m128i __A, __m128i __B)

VPSRAQ xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_srai_epi64 __m128i _mm_maskz_srai_epi64(__mmask8 __U, __m128i __A, unsigned int __imm)

VPSRAQ xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vlwith __imm a constant

_mm256_sra_epi64 __m256i _mm256_sra_epi64(__m256i __A, __m128i __B)

VPSRAQ ymm, ymm, xmm EVEX.256 -mavx512vl

_mm256_srai_epi64 __m256i _mm256_srai_epi64(__m256i __A, unsigned int __imm)

VPSRAQ ymm, ymm, imm8 EVEX.256 -mavx512vlwith __imm a constant

_mm256_mask_sra_epi64 __m256i _mm256_mask_sra_epi64(__m256i __W, __mmask8 __U, __m256i __A, __m128i __B)

VPSRAQ ymm {k}, ymm, xmm EVEX.256 -mavx512vl

_mm256_mask_srai_epi64 __m256i _mm256_mask_srai_epi64(__m256i __W, __mmask8 __U, __m256i __A, unsigned int __imm)

VPSRAQ ymm {k}, ymm, imm8 EVEX.256 -mavx512vlwith __imm a constant

_mm256_maskz_sra_epi64 __m256i _mm256_maskz_sra_epi64(__mmask8 __U, __m256i __A, __m128i __B)

VPSRAQ ymm {k}{z}, ymm, xmm EVEX.256 -mavx512vl

_mm256_maskz_srai_epi64 __m256i _mm256_maskz_srai_epi64(__mmask8 __U, __m256i __A, unsigned int __imm)

VPSRAQ ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vlwith __imm a constant

_mm512_sra_epi64 __m512i _mm512_sra_epi64(__m512i __A, __m128i __B)

VPSRAQ zmm, zmm, xmm EVEX.512 -mavx512f

_mm512_srai_epi64 __m512i _mm512_srai_epi64(__m512i __A, unsigned int __B)

VPSRAQ zmm, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

_mm512_mask_sra_epi64 __m512i _mm512_mask_sra_epi64(__m512i __W, __mmask8 __U, __m512i __A, __m128i __B)

VPSRAQ zmm {k}, zmm, xmm EVEX.512 -mavx512f

_mm512_mask_srai_epi64 __m512i _mm512_mask_srai_epi64(__m512i __W, __mmask8 __U, __m512i __A, unsigned int __B)

VPSRAQ zmm {k}, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

_mm512_maskz_sra_epi64 __m512i _mm512_maskz_sra_epi64(__mmask8 __U, __m512i __A, __m128i __B)

VPSRAQ zmm {k}{z}, zmm, xmm EVEX.512 -mavx512f

_mm512_maskz_srai_epi64 __m512i _mm512_maskz_srai_epi64(__mmask8 __U, __m512i __A, unsigned int __B)

VPSRAQ zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.