VPSRAVD

VPSRAVD shifts each doubleword right arithmetically by its own count, taken from the matching element of the second source, where VPSRAD shifts every element by the same one. AVX2 introduced it with VPSLLVD and VPSRLVD; AVX-512 added masking, a broadcast count, and the 512-bit form.

Counts out of range#

Each count is read as a whole unsigned doubleword, not masked to 5 bits as SAR masks its count: from 32 up, the element becomes all copies of its sign bit, 0 or -1, and a count of -1 is FFFFFFFFh, a very large shift. C leaves a >> b undefined for such counts, which lets a compiler map it to VPSRAVD directly: GCC 14 and Clang 23 at -O2 compile a >> b on vectors of int32_t to one VPSRAVD with -mavx2, and Clang vectorizes the loop d[i] = a[i] >> b[i] into it. Code that wants SAR’s wrap-around must AND the counts with 31 first.

The sizes AVX2 lacks#

AVX2 has the variable arithmetic shift for doublewords only. With -mavx2, a >> b on int64_t elements becomes a logical VPSRLVQ of the value and of the sign bit, an XOR and a subtraction that extend the sign again; on int16_t elements Clang widens to doublewords with unpacks, shifts with VPSRAVD and packs back, and GCC goes element by element. AVX-512 adds both missing sizes, and with -march=x86-64-v4 each becomes one instruction: VPSRAVQ in AVX-512F and VPSRAVW in AVX512BW.

A per-element count is how vector code extracts signed fields of different positions and widths: shift each field to the top with VPSLLVD, then down with VPSRAVD, which brings the sign along.

AMD’s Zen 5 guide lists VPSRAVD, VEX or EVEX, as one macro-op with a latency of one cycle, while VPSRAD takes two with its count in an XMM register, and with an immediate count two in its VEX form and one in its EVEX form.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = zmm2.sd[i] >> src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRAVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSHRDD
• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ

All 686 AVX10.1 instructions