VPSRAVQ

VPSRAVQ shifts each quadword right arithmetically by its own count, taken from the matching quadword of the second source. VPSRAVD describes the variable shifts, their counts read as whole unsigned elements, and the sequence that AVX2 code needs in place of this one. Unlike the doubleword form, this one has no VEX encoding: AVX2 has no arithmetic right shift of quadwords at all, by a variable count or by an immediate. It came with AVX-512F, with masking, a broadcast count and the 512-bit width.

Counts from 64 up#

Any count above 63 fills the element with copies of its sign bit, as a shift by 63 does. In the cases recorded on Zen 5, 8000000000000000h shifted by 3Fh gave all ones, and 7FFFFFFFFFFFFFFFh shifted by 40h gave 0, where SAR, which masks its count to six bits, would have left it unchanged. With a broadcast count of 3Fh, vpsravq zmm1{k3}, zmm2, qword bcst [mem] turned the six elements K3 selects into 0 or -1 by their signs and kept the other two.

Without it#

Even a constant count takes a sequence on AVX2: with -march=x86-64-v3, GCC 14 and Clang 23 at -O2 compile a >> 5 on vectors of int64_t to a logical VPSRLQ and an arithmetic VPSRAD by 5 and a VPBLENDD that takes the upper doublewords from the latter, and a >> 63 to a VPCMPGTQ against zero. With -march=x86-64-v4 each is one VPSRAQ with an immediate, and a >> b is one VPSRAVQ.

For d[i] = a[i] >> b[i] over int64_t arrays at -march=x86-64-v4, Clang emits VPSRAVQ with the counts read from memory, and it uses VPSRAVQ with a broadcast count even where every element shifts by the same s; GCC keeps both loops scalar with SARX at -O2. Clang also vectorizes the sign extension of a field w[i] bits wide, (a[i] << (64 - w[i])) >> (64 - w[i]), as VPSLLVQ followed by VPSRAVQ.

AMD’s latency spreadsheet for Zen 5 lists VPSRAVQ as it lists VPSRAVD: one macro-op with a latency of one cycle, on FP2 and FP3.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = zmm2.sq[i] >> src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRAVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSHRDQ
• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB

All 686 AVX10.1 instructions