VPSRAVW

VPSRAVW shifts each word right arithmetically by its own count, taken from the matching word of the second source: 8, 16 or 32 words at a time. It is the word form of VPSRAVD, whose page explains the counts read as whole unsigned elements and what AVX2 code does without this one; VPSRLVW is the logical form. It came with AVX512BW, in EVEX encodings only, with masking and the 512-bit width; AVX2 has variable shifts of doublewords and quadwords, but none of words.

Recorded on Zen 5#

• Counts in range. {evex} vpsravw xmm7, xmm12, xmm7 shifted 7FFFh by 1 to 3FFFh and 8000h by 15 to FFFFh, and left FFFFh as it was for a count of 0.
• Counts of 16 and more. 8000h shifted by 16 or 31 gave FFFFh, and 7FFFh shifted by 17 gave 0: every bit becomes a copy of the sign. A count of FFFFh, which is -1 as a signed word, did the same, so 7FFFh and 1 became 0.
• One register three times. vpsravw zmm5{k5}, zmm5, zmm5 shifted each selected word by itself and kept the others: 0010h became 0 and FFFFh stayed FFFFh.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile r[i] = h[i] >> (c[i] & 15) over int16_t arrays to VPANDQ or VPAND and VPSRAVW, GCC on ZMM registers and Clang on YMM registers. Without the AND, h[i] >> c[i], which C evaluates on int after promotion, neither uses VPSRAVW: GCC sign-extends both to doublewords with VPMOVSXWD, shifts with VPSRAVD and narrows with VPERMT2W, and Clang shifts doublewords and packs with VPACKSSDW and VPERMQ. _mm512_srav_epi16 is one VPSRAVW.

AMD’s Zen 5 latency spreadsheet gives VPSRAVW one macro-op on pipe FP2 or FP3 with a latency of one cycle, at every width.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.w[i] = zmm2.sw[i] >> src3.w[i]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRAVW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSHRDVD
• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD

All 686 AVX10.1 instructions