VPSRAW

VPSRAW shifts each word right by one shared count, copying its sign bit into the vacated bits: the VEX and EVEX form of PSRAW, whose page covers the operation, with the operands of VPSRAD. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms belong to AVX512BW, not AVX-512F, and like the other integer word instructions have masking but no broadcast, so their immediate form reads a whole vector from memory. A count of 16 or more leaves each word all sign. Zen 5’s recorded cases show both: vpsraw ymm8, ymm15, 0xff turned each of the sixteen words into 0000h or FFFFh, and vpsraw zmm5{k5}, zmmword ptr [mem], 0x11 did the same to the words k5 selects, straight from memory. With a count of 1, vpsraw ymm7, ymm11, [mem] turned 8000h into C000h and 7FFFh into 3FFFh in both lanes.

In compiled code#

In our builds at -O2, GCC 14 and Clang 23:

• Division by 4 over int16_t. Clang adds the bias from VPSRAW by 15 and VPSRLW by 14 before VPSRAW by 2 at -march=x86-64-v3 and -v4; GCC uses VPCMPGTW and a VPAND at -v3, and at -v4 a compare into a mask register and a zero-masked VMOVDQU16.
• Signed bytes. b[i] >> 3 over int8_t shifts words, GCC with VPSRAW and Clang with VPSRLW, keeps the five valid bits of each byte and extends their sign with an XOR and a subtraction of 10h. At -v4, one VPTERNLOGD or VPTERNLOGQ does the AND and the XOR.
• Signed averages. For (b[i] + c[i] + 1) >> 1, Clang computes (b | c) - ((b ^ c) >> 1) with VPSRAW at both levels, while GCC widens to doublewords and shifts with VPSRAD.

AMD’s latency spreadsheet for Zen 5 gives the EVEX immediate form one cycle on pipes FP2 and FP3 and the count from a register two cycles on FP0 and FP1, the figure its one row for the VEX forms gives them all. AVX512BW’s VPSRAVW takes a count per word.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

count = src3.q[0]
for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        zmm1.w[i] = zmm2.sw[i] >> count
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        zmm1.w[i] = src2.sw[i] >> imm8
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VPSRAW xmm, xmm, xmm/m128 VPSRAW xmm, xmm, imm8 VPSRAW ymm, ymm, imm8

avx-type-7

VPSRAW ymm, ymm, xmm/m128

avx-type-4

VPSRAW xmm {k}{z}, xmm/m128, imm8 VPSRAW ymm {k}{z}, ymm/m256, imm8 VPSRAW zmm {k}{z}, zmm/m512, imm8

AVX512-E4

VPSRAW xmm {k}{z}, xmm, xmm/m128 VPSRAW ymm {k}{z}, ymm, xmm/m128 VPSRAW zmm {k}{z}, zmm, xmm/m128

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

VPSRAW xmm {k}{z}, m128, imm8 VPSRAW ymm {k}{z}, m256, imm8 VPSRAW zmm {k}{z}, m512, imm8

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRAW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLW
• VPSRAD
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ

All 253 AVX instructions

More AVX2 instructions

• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSHRDVQ
• VPSHRDVW
• VPSHRDW
• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ

All 686 AVX10.1 instructions