x86-64.net

Instruction

VPSRLD

Shifts doublewords right logically by one count from a register or an immediate.

Extensions
Forms
18 (6 VEX, 12 EVEX)
Data
Intel XED v2026.08.23

VPSRLD shifts each doubleword right by one shared count, filling with zeros: the VEX and EVEX form of PSRLD, with the operands, widths, masking and broadcast that VPSLLD’s page describes. The count is still read whole, from an immediate or the low quadword of an XMM register or of memory, and anything above 31 clears the element. Zen 5’s recorded cases show it: vpsrld xmm8, xmm15, xmm0, whose count quadword was 0000000100000001h, cleared every element, where its low doubleword alone would have meant a shift by 1; vpsrld ymm4, ymm4, 0x3f cleared all eight; and vpsrld zmm17{k3}, dword bcst [mem], 0x1f turned the broadcast FFFFFFFFh into 1 in the ten elements k3 selects, keeping the other six. The XMM cases zeroed bits 511:128 of the destination.

In compiled code

In our builds at -O2 with -march=x86-64-v3, over uint32_t arrays:

  • Unsigned to float. AVX2 still converts only signed doublewords. For (float)b[i], GCC 14 splits each element with a VPAND of FFFFh and VPSRLD by 16, converts both halves with VCVTDQ2PS and joins them in one VFMADD132PS by 65536.0. With -march=x86-64-v4, GCC 14 and Clang 23 use AVX-512’s VCVTUDQ2PS instead.
  • Narrowing. Storing b[i] >> 16 as uint16_t is VPSRLD and VPACKUSDW in both, which packs within each 128-bit lane, so GCC reorders the quadwords with VPERMQ and Clang packs the two halves after VEXTRACTI128. At -v4, Clang stores the shifted words with VPMOVDW, and GCC gathers them with VPERMT2W.
  • A count in a variable. b[i] >> n moves n in with VMOVD for VPSRLD in GCC; Clang broadcasts it for VPSRLVD.

AMD’s latency spreadsheet for Zen 5 gives the EVEX immediate form one cycle on pipes FP2 and FP3 and the count from a register two cycles on FP0 and FP1, the figure its one row for the VEX forms gives them all.

Forms

Every encoding of VPSRLD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSRLD xmm, xmm, m128 VPSRLD_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG D2 /rAVX
VPSRLD xmm, xmm, xmm VPSRLD_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG D2 /rAVX
VPSRLD xmm, xmm, imm8 VPSRLD_XMMdq_XMMdq_IMMbVEX.128.66.0F.WIG 72 /2 ibAVX
VPSRLD ymm, ymm, m128 VPSRLD_YMMqq_YMMqq_MEMdqVEX.256.66.0F.WIG D2 /rAVX2
VPSRLD ymm, ymm, xmm VPSRLD_YMMqq_YMMqq_XMMqVEX.256.66.0F.WIG D2 /rAVX2
VPSRLD ymm, ymm, imm8 VPSRLD_YMMqq_YMMqq_IMMbVEX.256.66.0F.WIG 72 /2 ibAVX2
VPSRLD zmm {k}{z}, zmm, xmm VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512EVEX.512.66.0F.W0 D2 /rAVX10.1 or AVX512F
VPSRLD zmm {k}{z}, zmm, m128 VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512EVEX.512.66.0F.W0 D2 /rAVX10.1 or AVX512F
VPSRLD zmm {k}{z}, zmm, imm8 VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512EVEX.512.66.0F.W0 72 /2 ibAVX10.1 or AVX512F
VPSRLD zmm {k}{z}, m512/m32bcst, imm8 VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.512.66.0F.W0 72 /2 ibAVX10.1 or AVX512F
VPSRLD xmm {k}{z}, xmm, imm8 VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512EVEX.128.66.0F.W0 72 /2 ibAVX10.1 or AVX512F + AVX512VL
VPSRLD xmm {k}{z}, m128/m32bcst, imm8 VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.128.66.0F.W0 72 /2 ibAVX10.1 or AVX512F + AVX512VL
VPSRLD xmm {k}{z}, xmm, xmm VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512EVEX.128.66.0F.W0 D2 /rAVX10.1 or AVX512F + AVX512VL
VPSRLD xmm {k}{z}, xmm, m128 VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512EVEX.128.66.0F.W0 D2 /rAVX10.1 or AVX512F + AVX512VL
VPSRLD ymm {k}{z}, ymm, imm8 VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512EVEX.256.66.0F.W0 72 /2 ibAVX10.1 or AVX512F + AVX512VL
VPSRLD ymm {k}{z}, m256/m32bcst, imm8 VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512EVEX.256.66.0F.W0 72 /2 ibAVX10.1 or AVX512F + AVX512VL
VPSRLD ymm {k}{z}, ymm, xmm VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512EVEX.256.66.0F.W0 D2 /rAVX10.1 or AVX512F + AVX512VL
VPSRLD ymm {k}{z}, ymm, m128 VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512EVEX.256.66.0F.W0 D2 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm		xmm, xmm, imm8ymm, ymm, m128
ymm {k}{z}, m256/m32bcst, imm8
ymm {k}{z}, ymm, m128		ymm, ymm, xmm
ymm {k}{z}, ymm, xmm		ymm, ymm, imm8zmm {k}{z}, zmm, xmmzmm {k}{z}, zmm, m128
zmm {k}{z}, m512/m32bcst, imm8		zmm {k}{z}, zmm, imm8xmm {k}{z}, xmm, imm8
ymm {k}{z}, ymm, imm8		xmm {k}{z}, m128/m32bcst, imm8
Sandy Bridge8 / 1p0152 / 1p0151 / 1p0
Haswell8 / 1p02 / 1p051 / 1p08 / 1p04 / 1p051 / 1p0
Broadwell7 / 1p02 / 1p051 / 1p07 / 1p04 / 1p051 / 1p0
Skylake7 / 0.5p012 / 1p0151 / 0.5p018 / 0.5p014 / 1p0151 / 0.5p01
Skylake-SP7 / 0.5p012 / 1p0151 / 0.5p018 / 0.5p014 / 1p0151 / 0.5p014 / 1p058 / 1p01 / 1p01 / 0.5p017 / 0.5p01
Ice Lake7 / 0.5p012 / 0.67p0151 / 0.5p018 / 0.5p014 / 1p0151 / 0.5p014 / 1p058 / 1p01 / 1p01 / 0.5p017 / 0.5p01
Alder Lake8 / 0.5p012 / 0.67p0151 / 0.5p019 / 0.5p014 / 1p0151 / 0.5p01
Sapphire Rapids8 / 0.5p012 / 0.67p0151 / 0.5p019 / 0.5p014 / 1p0151 / 0.5p014 / 1p059 / 1p01 / 1p01 / 0.5p018 / 0.5p01
Lunar Lake8 / 0.5V0 V12 / 0.5V0 V1 V2 V31 / 0.5V0 V19 / 2.33V0 V14 / 0.5V0 V1 V2 V31 / 0.5V0 V1
Piledriver8 / 1.5FPU1 FPXBR3 / 1FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 1FPU21 / 1FPU21 / 1FPU28 / 2FPU21 / 2FPU21 / 2FPU2
Zen 28 / 1FPU21 / 1FPU21 / 1FPU28 / 1FPU21 / 1FPU21 / 1FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 49 / 1FP1 FP22 / 11FP0 FP11 / 0.5FP1 FP28 / 0.5FP1 FP22 / 12FP0 FP11 / 0.5FP1 FP22 / 1FP0 FP18 / 1FP1 FP21 / 0.5FP0 FP11 / 0.5FP0 FP18 / 0.5FP1 FP2
Jaguar7 / 1FPU0 FPU1 VALU0 VALU12 / 0.5FPU0 FPU1 VALU0 VALU12 / 0.5FPU0 FPU1 VALU0 VALU1
  1. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2977; AMD 58455, row 1177).
  2. Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 2981; AMD 58455, row 1177).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise, by one count: each doubleword is shifted by the count in the low 64 bits of xmm3.VPSRLD xmm, xmm, xmm/m128 VPSRLD ymm, ymm, xmm/m128 VPSRLD xmm {k}{z}, xmm, xmm/m128 VPSRLD ymm {k}{z}, ymm, xmm/m128 VPSRLD zmm {k}{z}, zmm, xmm/m128
VPSRLD: element by elementResult doubleword i comes from doubleword i of xmm2 and the count in xmm3. Result doublewords 3 to 0: r3, unchanged (bit 2 of k1 is 0), r1, r0.0123xmm2a1110k1r0r1r3xmm1countxmm3or m128c

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result doubleword i comes from doubleword i of xmm2 and the count in xmm3. Result doublewords 3 to 0: r3, unchanged (bit 2 of k1 is 0), r1, r0.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.VPSRLD xmm, xmm, imm8 VPSRLD ymm, ymm, imm8 VPSRLD xmm {k}{z}, xmm/m128/m32bcst, imm8 VPSRLD ymm {k}{z}, ymm/m256/m32bcst, imm8 VPSRLD zmm {k}{z}, zmm/m512/m32bcst, imm8
VPSRLD: element by elementResult doubleword i comes from doubleword i of xmm2. Result doublewords 3 to 0: r3, unchanged (bit 2 of k1 is 0), r1, r0.xmm2or m128a

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of the last source.

Result doubleword i comes from doubleword i of xmm2. Result doublewords 3 to 0: r3, unchanged (bit 2 of k1 is 0), r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VPSRLD xmm, xmm, xmm/m128 VPSRLD ymm, ymm, xmm/m128 VPSRLD xmm {k}{z}, xmm, xmm/m128 VPSRLD ymm {k}{z}, ymm, xmm/m128 VPSRLD zmm {k}{z}, zmm, xmm/m128
count = src3.q[0]
for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = zmm2.d[i] >> count
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

VPSRLD xmm, xmm, imm8 VPSRLD ymm, ymm, imm8 VPSRLD xmm {k}{z}, xmm/m128/m32bcst, imm8 VPSRLD ymm {k}{z}, ymm/m256/m32bcst, imm8 VPSRLD zmm {k}{z}, zmm/m512/m32bcst, imm8
for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src2.d[i] >> imm8
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPSRLD xmm, xmm, xmm/m128 VPSRLD ymm, ymm, xmm/m128
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128explicitread
VPSRLD xmm, xmm, imm8 VPSRLD ymm, ymm, imm8
xmm, ymmexplicitwrite
xmm, ymmexplicitread
imm8explicitread
VPSRLD xmm {k}{z}, xmm, xmm/m128 VPSRLD ymm {k}{z}, ymm, xmm/m128 VPSRLD zmm {k}{z}, zmm, xmm/m128
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128explicitread
VPSRLD xmm {k}{z}, xmm/m128/m32bcst, imm8 VPSRLD ymm {k}{z}, ymm/m256/m32bcst, imm8 VPSRLD zmm {k}{z}, zmm/m512/m32bcst, imm8
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread
imm8explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VPSRLD xmm, xmm, xmm/m128 VPSRLD xmm, xmm, imm8 VPSRLD ymm, ymm, imm8
avx-type-7
VPSRLD ymm, ymm, xmm/m128
avx-type-4
VPSRLD xmm {k}{z}, xmm, xmm/m128 VPSRLD ymm {k}{z}, ymm, xmm/m128 VPSRLD zmm {k}{z}, zmm, xmm/m128
AVX512-E4NF
VPSRLD xmm {k}{z}, xmm/m128/m32bcst, imm8 VPSRLD ymm {k}{z}, ymm/m256/m32bcst, imm8 VPSRLD zmm {k}{z}, zmm/m512/m32bcst, imm8
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
VPSRLD xmm {k}{z}, m128/m32bcst, imm8 VPSRLD ymm {k}{z}, m256/m32bcst, imm8 VPSRLD zmm {k}{z}, m512/m32bcst, imm8
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRLD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_srl_epi32 __m128i _mm_srl_epi32(__m128i __a, __m128i __count)

VPSRLD xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_srli_epi32 __m128i _mm_srli_epi32(__m128i __a, int __count)

VPSRLD xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled; with __count a constant

_mm_mask_srl_epi32 __m128i _mm_mask_srl_epi32(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPSRLD xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_srli_epi32 __m128i _mm_mask_srli_epi32(__m128i __W, __mmask8 __U, __m128i __A, unsigned int __B)

VPSRLD xmm {k}, xmm, imm8 EVEX.128 -mavx512vlwith __B a constant

_mm_maskz_srl_epi32 __m128i _mm_maskz_srl_epi32(__mmask8 __U, __m128i __A, __m128i __B)

VPSRLD xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_srli_epi32 __m128i _mm_maskz_srli_epi32(__mmask8 __U, __m128i __A, unsigned int __B)

VPSRLD xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vlwith __B a constant

_mm256_srl_epi32 __m256i _mm256_srl_epi32(__m256i __a, __m128i __count)

VPSRLD ymm, ymm, xmm VEX.256 -mavx2

_mm256_srli_epi32 __m256i _mm256_srli_epi32(__m256i __a, int __count)

VPSRLD ymm, ymm, imm8 VEX.256 -mavx2with __count a constant

_mm256_mask_srl_epi32 __m256i _mm256_mask_srl_epi32(__m256i __W, __mmask8 __U, __m256i __A, __m128i __B)

VPSRLD ymm {k}, ymm, xmm EVEX.256 -mavx512vl

_mm256_mask_srli_epi32 __m256i _mm256_mask_srli_epi32(__m256i __W, __mmask8 __U, __m256i __A, unsigned int __B)

VPSRLD ymm {k}, ymm, imm8 EVEX.256 -mavx512vlwith __B a constant

_mm256_maskz_srl_epi32 __m256i _mm256_maskz_srl_epi32(__mmask8 __U, __m256i __A, __m128i __B)

VPSRLD ymm {k}{z}, ymm, xmm EVEX.256 -mavx512vl

_mm256_maskz_srli_epi32 __m256i _mm256_maskz_srli_epi32(__mmask8 __U, __m256i __A, unsigned int __B)

VPSRLD ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vlwith __B a constant

_mm512_srl_epi32 __m512i _mm512_srl_epi32(__m512i __A, __m128i __B)

VPSRLD zmm, zmm, xmm EVEX.512 -mavx512f

_mm512_srli_epi32 __m512i _mm512_srli_epi32(__m512i __A, unsigned int __B)

VPSRLD zmm, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

_mm512_mask_srl_epi32 __m512i _mm512_mask_srl_epi32(__m512i __W, __mmask16 __U, __m512i __A, __m128i __B)

VPSRLD zmm {k}, zmm, xmm EVEX.512 -mavx512f

_mm512_mask_srli_epi32 __m512i _mm512_mask_srli_epi32(__m512i __W, __mmask16 __U, __m512i __A, unsigned int __B)

VPSRLD zmm {k}, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

_mm512_maskz_srl_epi32 __m512i _mm512_maskz_srl_epi32(__mmask16 __U, __m512i __A, __m128i __B)

VPSRLD zmm {k}{z}, zmm, xmm EVEX.512 -mavx512f

_mm512_maskz_srli_epi32 __m512i _mm512_maskz_srli_epi32(__mmask16 __U, __m512i __A, unsigned int __B)

VPSRLD zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-467 (PSRLW/PSRLD/PSRLQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.