VPSRLQ

VPSRLQ shifts each quadword right by one shared count, filling with zeros: the VEX and EVEX form of PSRLQ, with the operands, masking and quadword broadcast that VPSLLQ’s page describes. Any count above 63 clears the element, and the count is the whole low quadword of its register or memory: on Zen 5, the recorded vpsrlq ymm0, ymm13, [mem] read 0000000100000001h and cleared all four quadwords. With a count of 1, vpsrlq zmm9{k3}, zmm9, [mem] turned 8000000000000000h into 4000000000000000h, no sign copied, in the six elements k3 selects, and vpsrlq zmm9{k2}, qword bcst [mem], 0x7f cleared the four that k2 selects.

In compiled code#

In our builds at -O2 with -march=x86-64-v3, GCC 14 and Clang 23:

• High halves. a[i] = b[i] >> 32 from uint64_t into uint32_t is VPSRLQ by 32 in GCC, followed by VPERM2I128, VPSHUFD and VPUNPCKLQDQ to gather the doublewords across the lanes; Clang picks the odd doublewords with one VPERMPS and shifts nothing. With -march=x86-64-v4 both shift straight from memory, then Clang stores with VPMOVQD and GCC gathers with VPERMT2D.
• Signed quadwords. b[i] >> 5 over int64_t is VPSRLQ of the whole quadwords, VPSRAD of the high halves and a VPBLENDD at -v3, and one VPSRAQ at -v4.
• Conversions. For uint64_t to double, Clang places the high half, brought down by VPSRLQ by 32, and the low half in the significands of two constants with VPOR, subtracts the constants with VSUBPD and adds the halves with VADDPD; GCC converts one element at a time. At -v4 both use VCVTUQQ2PD.

AMD’s latency spreadsheet for Zen 5 gives the EVEX immediate form one cycle on pipes FP2 and FP3 and the count from a register two cycles on FP0 and FP1, the figure its one row for the VEX forms gives them all. AVX2’s VPSRLVQ takes a count per element.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

count = src3.q[0]
for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = zmm2.q[i] >> count
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = src2.q[i] >> imm8
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VPSRLQ xmm, xmm, xmm/m128 VPSRLQ xmm, xmm, imm8 VPSRLQ ymm, ymm, imm8

avx-type-7

VPSRLQ ymm, ymm, xmm/m128

avx-type-4

VPSRLQ xmm {k}{z}, xmm, xmm/m128 VPSRLQ ymm {k}{z}, ymm, xmm/m128 VPSRLQ zmm {k}{z}, zmm, xmm/m128

AVX512-E4NF

VPSRLQ xmm {k}{z}, xmm/m128/m64bcst, imm8 VPSRLQ ymm {k}{z}, ymm/m256/m64bcst, imm8 VPSRLQ zmm {k}{z}, zmm/m512/m64bcst, imm8

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

VPSRLQ xmm {k}{z}, m128/m64bcst, imm8 VPSRLQ ymm {k}{z}, m256/m64bcst, imm8 VPSRLQ zmm {k}{z}, m512/m64bcst, imm8

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRLQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS

All 253 AVX instructions

More AVX2 instructions

• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSHUFB
• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD

All 686 AVX10.1 instructions