x86-64.net

Instruction

VPSRLQ

Shifts quadwords right logically by one count from a register or an immediate.

Extensions
Forms
18 (6 VEX, 12 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPSRLQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSRLQ xmm, xmm, m128 VPSRLQ_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG D3 /rAVX
VPSRLQ xmm, xmm, xmm VPSRLQ_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG D3 /rAVX
VPSRLQ xmm, xmm, imm8 VPSRLQ_XMMdq_XMMdq_IMMbVEX.128.66.0F.WIG 73 /2 ibAVX
VPSRLQ ymm, ymm, m128 VPSRLQ_YMMqq_YMMqq_MEMdqVEX.256.66.0F.WIG D3 /rAVX2
VPSRLQ ymm, ymm, xmm VPSRLQ_YMMqq_YMMqq_XMMqVEX.256.66.0F.WIG D3 /rAVX2
VPSRLQ ymm, ymm, imm8 VPSRLQ_YMMqq_YMMqq_IMMbVEX.256.66.0F.WIG 73 /2 ibAVX2
VPSRLQ zmm {k}{z}, zmm, xmm VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512EVEX.512.66.0F.W1 D3 /rAVX10.1 or AVX512F
VPSRLQ zmm {k}{z}, zmm, m128 VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512EVEX.512.66.0F.W1 D3 /rAVX10.1 or AVX512F
VPSRLQ zmm {k}{z}, zmm, imm8 VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512EVEX.512.66.0F.W1 73 /2 ibAVX10.1 or AVX512F
VPSRLQ zmm {k}{z}, m512/m64bcst, imm8 VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512EVEX.512.66.0F.W1 73 /2 ibAVX10.1 or AVX512F
VPSRLQ xmm {k}{z}, xmm, imm8 VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512EVEX.128.66.0F.W1 73 /2 ibAVX10.1 or AVX512F + AVX512VL
VPSRLQ xmm {k}{z}, m128/m64bcst, imm8 VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512EVEX.128.66.0F.W1 73 /2 ibAVX10.1 or AVX512F + AVX512VL
VPSRLQ xmm {k}{z}, xmm, xmm VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512EVEX.128.66.0F.W1 D3 /rAVX10.1 or AVX512F + AVX512VL
VPSRLQ xmm {k}{z}, xmm, m128 VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512EVEX.128.66.0F.W1 D3 /rAVX10.1 or AVX512F + AVX512VL
VPSRLQ ymm {k}{z}, ymm, imm8 VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512EVEX.256.66.0F.W1 73 /2 ibAVX10.1 or AVX512F + AVX512VL
VPSRLQ ymm {k}{z}, m256/m64bcst, imm8 VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512EVEX.256.66.0F.W1 73 /2 ibAVX10.1 or AVX512F + AVX512VL
VPSRLQ ymm {k}{z}, ymm, xmm VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512EVEX.256.66.0F.W1 D3 /rAVX10.1 or AVX512F + AVX512VL
VPSRLQ ymm {k}{z}, ymm, m128 VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512EVEX.256.66.0F.W1 D3 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRLQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_srl_epi64 __m128i _mm_srl_epi64(__m128i __a, __m128i __count)

VPSRLQ xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_srli_epi64 __m128i _mm_srli_epi64(__m128i __a, int __count)

VPSRLQ xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled; with __count a constant

_mm_mask_srl_epi64 __m128i _mm_mask_srl_epi64(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPSRLQ xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_srli_epi64 __m128i _mm_mask_srli_epi64(__m128i __W, __mmask8 __U, __m128i __A, unsigned int __B)

VPSRLQ xmm {k}, xmm, imm8 EVEX.128 -mavx512vlwith __B a constant

_mm_maskz_srl_epi64 __m128i _mm_maskz_srl_epi64(__mmask8 __U, __m128i __A, __m128i __B)

VPSRLQ xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_srli_epi64 __m128i _mm_maskz_srli_epi64(__mmask8 __U, __m128i __A, unsigned int __B)

VPSRLQ xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vlwith __B a constant

_mm256_srl_epi64 __m256i _mm256_srl_epi64(__m256i __a, __m128i __count)

VPSRLQ ymm, ymm, xmm VEX.256 -mavx2

_mm256_srli_epi64 __m256i _mm256_srli_epi64(__m256i __a, int __count)

VPSRLQ ymm, ymm, imm8 VEX.256 -mavx2with __count a constant

_mm256_mask_srl_epi64 __m256i _mm256_mask_srl_epi64(__m256i __W, __mmask8 __U, __m256i __A, __m128i __B)

VPSRLQ ymm {k}, ymm, xmm EVEX.256 -mavx512vl

_mm256_mask_srli_epi64 __m256i _mm256_mask_srli_epi64(__m256i __W, __mmask8 __U, __m256i __A, unsigned int __B)

VPSRLQ ymm {k}, ymm, imm8 EVEX.256 -mavx512vlwith __B a constant

_mm256_maskz_srl_epi64 __m256i _mm256_maskz_srl_epi64(__mmask8 __U, __m256i __A, __m128i __B)

VPSRLQ ymm {k}{z}, ymm, xmm EVEX.256 -mavx512vl

_mm256_maskz_srli_epi64 __m256i _mm256_maskz_srli_epi64(__mmask8 __U, __m256i __A, unsigned int __B)

VPSRLQ ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vlwith __B a constant

_mm512_srl_epi64 __m512i _mm512_srl_epi64(__m512i __A, __m128i __B)

VPSRLQ zmm, zmm, xmm EVEX.512 -mavx512f

_mm512_srli_epi64 __m512i _mm512_srli_epi64(__m512i __A, unsigned int __B)

VPSRLQ zmm, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

_mm512_mask_srl_epi64 __m512i _mm512_mask_srl_epi64(__m512i __W, __mmask8 __U, __m512i __A, __m128i __B)

VPSRLQ zmm {k}, zmm, xmm EVEX.512 -mavx512f

_mm512_mask_srli_epi64 __m512i _mm512_mask_srli_epi64(__m512i __W, __mmask8 __U, __m512i __A, unsigned int __B)

VPSRLQ zmm {k}, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

_mm512_maskz_srl_epi64 __m512i _mm512_maskz_srl_epi64(__mmask8 __U, __m512i __A, __m128i __B)

VPSRLQ zmm {k}{z}, zmm, xmm EVEX.512 -mavx512f

_mm512_maskz_srli_epi64 __m512i _mm512_maskz_srli_epi64(__mmask8 __U, __m512i __A, unsigned int __B)

VPSRLQ zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512fwith __B a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.