VPSRLVD

VPSRLVD shifts each doubleword right by its own count, taken from the matching doubleword of the second source, and fills with zeros from the left. VPSLLVD describes the variable shifts of AVX2 and AVX-512: whole unsigned counts, zero for every count from 32 up, and the compilers’ code without AVX2. VPSRAVD is the arithmetic twin, which fills with copies of the sign bit. On Zen 5, vpsrlvd ymm0, ymm13, ymm9 turned 80000000h shifted by 16 into 8000h and shifted by 3 into 10000000h, with zeros where VPSRAVD would bring in ones, and gave zero for counts 20h, 21h and 3Fh.

Fields at different positions#

A constant vector of counts takes apart a word whose fields sit at different bit positions. Splitting a 32-bit word into eight 4-bit fields, out[i] = (w >> 4 * i) & 15 for i from 0 to 7, compiles in GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 to three instructions: VPBROADCASTD of w, VPSRLVD by the vector 0, 4, 8 … 28 from memory, and VPAND with 15. Over an array of such words, GCC keeps that pattern for each word, while Clang turns the loop around: it shifts eight words at a time by each of the seven counts with VPSRLD and an immediate, and interleaves the results.

The plain a[i] = b[i] >> c[i] over uint32_t arrays is one VPSRLVD per vector in both compilers, on ZMM registers in GCC with -march=x86-64-v4. For the SSE2 baseline, Clang shifts each vector four times with PSRLD, once by each element’s count moved into place with PSHUFLW, and keeps the matching element of each result; GCC keeps the loop scalar with SHR.

AMD’s latency spreadsheet for Zen 5 lists VPSRLVD, VEX or EVEX, as one macro-op with a latency of one cycle on the pipes FP2 and FP3. The quadword form is VPSRLVQ.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = zmm2.d[i] >> src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRLVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSHUFBITQMB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ

All 686 AVX10.1 instructions