VPSRLVQ

VPSRLVQ shifts each quadword right by its own count, taken from the matching quadword of the second source, and fills with zeros from the left. It is the 64-bit, logical, rightward member of the variable shifts that AVX2 introduced; VPSLLVD and VPSRAVD describe the family, the counts read as whole unsigned elements, and what compilers do without AVX2. For quadwords, every count from 64 up gives zero: the cases recorded on Zen 5 show zero for counts of 65, 127 and FFFFFFFFFFFFFFFFh, where SHR would mask the count to its low 6 bits.

A bitmap lookup per element#

Shifting one 64-bit constant by many counts tests many bits of it at once. For d[i] = (m >> (x[i] & 63)) & 1, where m is a bitmap of 64 entries such as a set of character classes, GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 broadcast m and apply VPSRLVQ with the indices as counts, testing four entries per instruction, eight with zmm registers. The plain a[i] >> b[i] on uint64_t arrays becomes one VPSRLVQ per vector in both compilers; C leaves counts of 64 and more undefined, so the zero is never in the way.

Before AVX2#

SSE2’s PSRLQ with a register count shifts both quadwords by the same count, the low quadword of the count register. For the SSE2 baseline Clang 23 still vectorizes a[i] >> b[i]: it shifts the vector twice, once by each element’s count, and keeps one half of each result. GCC 14 keeps the loop scalar with SHR. AMD’s XOP had a variable shift of its own, VPSHLQ, whose signed count shifts left when positive and right when negative; Zen 5 has no XOP.

AVX-512 adds masking, a broadcast count and the 512-bit form, and the arithmetic VPSRAVQ, which AVX2 lacks. The left shift is VPSLLVQ. AMD’s Zen 5 guide lists VPSRLVQ, VEX or EVEX, as one macro-op with a latency of one cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = zmm2.q[i] >> src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRLVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW

All 686 AVX10.1 instructions