VPSRLVW

VPSRLVW shifts each word right by its own count, taken from the matching word of the second source, and fills with zeros from the left. It is the word form of VPSRLVD, added by AVX512BW; VPSLLVD describes the variable shifts, with whole unsigned counts and zero for every count from 16 up here. VPSRAVW is the arithmetic twin and VPSLLVW shifts left. It has no broadcast form.

Recorded on Zen 5#

• Zeros from the left. In vpsrlvw ymm9, ymm9, ymmword ptr [mem], 7FFFh shifted by 1 gave 3FFFh, 8000h by 15 gave 1 and FFFFh by 8 gave 00FFh, where VPSRAVW would have brought in ones for 8000h and FFFFh.
• Counts from 16. In vpsrlvw xmm9, xmm9, xmm14, FFFFh shifted by 11h and by FFFFh and 7FFFh by 8000h all gave 0; in the YMM case a count of 0 left FFFFh as it was.
• Zeroing. In vpsrlvw xmm24{k7}{z}, xmm3, xmmword ptr [mem], with E3h in K7’s low byte, FFFFh shifted by 8 gave 00FFh in word 6, and the words K7 left out were zeroed.

In compiled code#

For o[i] = a[i] >> (b[i] & 15) over uint16_t arrays, GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 mask the counts with a VPANDQ or VPAND and shift with VPSRLVW, GCC on ZMM and Clang on YMM registers. With -march=x86-64-v3, which has no shift of words by separate counts, GCC keeps the loop scalar with one SARX per element; for the left shift VPSLLVW’s page shows how GCC widens to doublewords instead.

AMD’s Zen 5 latency spreadsheet gives VPSRLVW one cycle and two per cycle on pipes FP2 and FP3, as VPSLLVW.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.w[i] = zmm2.w[i] >> src3.w[i]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRLVW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSHUFHW
• VPSHUFLW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW

All 686 AVX10.1 instructions