x86-64.net

Instruction

VPSRLW

Shifts words right logically by one count from a register or an immediate.

Extensions
Forms
18 (6 VEX, 12 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPSRLW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSRLW xmm, xmm, m128 VPSRLW_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG D1 /rAVX
VPSRLW xmm, xmm, xmm VPSRLW_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG D1 /rAVX
VPSRLW xmm, xmm, imm8 VPSRLW_XMMdq_XMMdq_IMMbVEX.128.66.0F.WIG 71 /2 ibAVX
VPSRLW ymm, ymm, m128 VPSRLW_YMMqq_YMMqq_MEMdqVEX.256.66.0F.WIG D1 /rAVX2
VPSRLW ymm, ymm, xmm VPSRLW_YMMqq_YMMqq_XMMqVEX.256.66.0F.WIG D1 /rAVX2
VPSRLW ymm, ymm, imm8 VPSRLW_YMMqq_YMMqq_IMMbVEX.256.66.0F.WIG 71 /2 ibAVX2
VPSRLW xmm {k}{z}, xmm, imm8 VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512EVEX.128.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW + AVX512VL
VPSRLW xmm {k}{z}, m128, imm8 VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512EVEX.128.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW + AVX512VL
VPSRLW xmm {k}{z}, xmm, xmm VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512EVEX.128.66.0F.WIG D1 /rAVX10.1 or AVX512BW + AVX512VL
VPSRLW xmm {k}{z}, xmm, m128 VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512EVEX.128.66.0F.WIG D1 /rAVX10.1 or AVX512BW + AVX512VL
VPSRLW ymm {k}{z}, ymm, imm8 VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512EVEX.256.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW + AVX512VL
VPSRLW ymm {k}{z}, m256, imm8 VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512EVEX.256.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW + AVX512VL
VPSRLW ymm {k}{z}, ymm, xmm VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512EVEX.256.66.0F.WIG D1 /rAVX10.1 or AVX512BW + AVX512VL
VPSRLW ymm {k}{z}, ymm, m128 VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512EVEX.256.66.0F.WIG D1 /rAVX10.1 or AVX512BW + AVX512VL
VPSRLW zmm {k}{z}, zmm, imm8 VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512EVEX.512.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW
VPSRLW zmm {k}{z}, m512, imm8 VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512EVEX.512.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW
VPSRLW zmm {k}{z}, zmm, xmm VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512EVEX.512.66.0F.WIG D1 /rAVX10.1 or AVX512BW
VPSRLW zmm {k}{z}, zmm, m128 VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512EVEX.512.66.0F.WIG D1 /rAVX10.1 or AVX512BW

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_srl_epi16 __m128i _mm_srl_epi16(__m128i __a, __m128i __count)

VPSRLW xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_srli_epi16 __m128i _mm_srli_epi16(__m128i __a, int __count)

VPSRLW xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled; with __count a constant

_mm_mask_srl_epi16 __m128i _mm_mask_srl_epi16(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPSRLW xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_mask_srli_epi16 __m128i _mm_mask_srli_epi16(__m128i __W, __mmask8 __U, __m128i __A, int __B)

VPSRLW xmm {k}, xmm, imm8 EVEX.128 -mavx512vl -mavx512bwwith __B a constant

_mm_maskz_srl_epi16 __m128i _mm_maskz_srl_epi16(__mmask8 __U, __m128i __A, __m128i __B)

VPSRLW xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_srli_epi16 __m128i _mm_maskz_srli_epi16(__mmask8 __U, __m128i __A, int __B)

VPSRLW xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vl -mavx512bwwith __B a constant

_mm256_srl_epi16 __m256i _mm256_srl_epi16(__m256i __a, __m128i __count)

VPSRLW ymm, ymm, xmm VEX.256 -mavx2

_mm256_srli_epi16 __m256i _mm256_srli_epi16(__m256i __a, int __count)

VPSRLW ymm, ymm, imm8 VEX.256 -mavx2with __count a constant

_mm256_mask_srl_epi16 __m256i _mm256_mask_srl_epi16(__m256i __W, __mmask16 __U, __m256i __A, __m128i __B)

VPSRLW ymm {k}, ymm, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_srli_epi16 __m256i _mm256_mask_srli_epi16(__m256i __W, __mmask16 __U, __m256i __A, int __B)

VPSRLW ymm {k}, ymm, imm8 EVEX.256 -mavx512vl -mavx512bwwith __B a constant

_mm256_maskz_srl_epi16 __m256i _mm256_maskz_srl_epi16(__mmask16 __U, __m256i __A, __m128i __B)

VPSRLW ymm {k}{z}, ymm, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_srli_epi16 __m256i _mm256_maskz_srli_epi16(__mmask16 __U, __m256i __A, int __B)

VPSRLW ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vl -mavx512bwwith __B a constant

_mm512_srl_epi16 __m512i _mm512_srl_epi16(__m512i __A, __m128i __B)

VPSRLW zmm, zmm, xmm EVEX.512 -mavx512bw

_mm512_srli_epi16 __m512i _mm512_srli_epi16(__m512i __A, unsigned int __B)

VPSRLW zmm, zmm, imm8 EVEX.512 -mavx512bwwith __B a constant

_mm512_mask_srl_epi16 __m512i _mm512_mask_srl_epi16(__m512i __W, __mmask32 __U, __m512i __A, __m128i __B)

VPSRLW zmm {k}, zmm, xmm EVEX.512 -mavx512bw

_mm512_mask_srli_epi16 __m512i _mm512_mask_srli_epi16(__m512i __W, __mmask32 __U, __m512i __A, unsigned int __B)

VPSRLW zmm {k}, zmm, imm8 EVEX.512 -mavx512bwwith __B a constant

_mm512_maskz_srl_epi16 __m512i _mm512_maskz_srl_epi16(__mmask32 __U, __m512i __A, __m128i __B)

VPSRLW zmm {k}{z}, zmm, xmm EVEX.512 -mavx512bw

_mm512_maskz_srli_epi16 __m512i _mm512_maskz_srli_epi16(__mmask32 __U, __m512i __A, int __B)

VPSRLW zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512bwwith __B a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.