x86-64.net

Instruction

VPSRLW

Shifts words right logically by one count from a register or an immediate.

Extensions
Forms
18 (6 VEX, 12 EVEX)
Data
Intel XED v2026.08.23

VPSRLW is the VEX and EVEX form of PSRLW, the logical right shift of every word by one count, with the count rules PSLLW gives for the family. The forms are VPSLLW’s: VEX.128 for AVX, VEX.256 for AVX2, and EVEX for AVX512BW or AVX10.1, with masking, the 512-bit width and a memory source for the immediate form, but no broadcast.

On Zen 5, vpsrlw ymm0, ymm13, 0x1 shifted all sixteen words alike, 8000h becoming 4000h in either lane; {evex} vpsrlw ymm0, ymm31, xmmword ptr [mem], with a count of 0, copied its source; and vpsrlw zmm24{k3}, zmm3, xmm3, by 15, brought the top bit of each word K3 selects down to bit 0 and kept the other words.

In compiled code

In our builds at -O2, b[i] >> 3 over uint16_t arrays is VPSRLW by 3 with -march=x86-64-v3 in GCC 14 and Clang 23, read straight from memory with -march=x86-64-v4. Over uint8_t arrays it is VPSRLW and a VPAND with 1Fh in every byte. Narrowing w[i] >> 8 to bytes is VPSRLW by 8 and VPACKUSWB at -v3, which packs within each 128-bit lane: GCC reorders the quadwords with VPERMQ, Clang packs the two halves of each register. At -v4 both narrow with AVX512BW’s VPMOVWB instead.

AMD’s latency spreadsheet for Zen 5 gives the EVEX immediate form one cycle on pipes FP2 and FP3 and the count from a register two cycles on FP0 and FP1, as its one VEX row gives every VEX form.

Forms

Every encoding of VPSRLW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSRLW xmm, xmm, m128 VPSRLW_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG D1 /rAVX
VPSRLW xmm, xmm, xmm VPSRLW_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG D1 /rAVX
VPSRLW xmm, xmm, imm8 VPSRLW_XMMdq_XMMdq_IMMbVEX.128.66.0F.WIG 71 /2 ibAVX
VPSRLW ymm, ymm, m128 VPSRLW_YMMqq_YMMqq_MEMdqVEX.256.66.0F.WIG D1 /rAVX2
VPSRLW ymm, ymm, xmm VPSRLW_YMMqq_YMMqq_XMMqVEX.256.66.0F.WIG D1 /rAVX2
VPSRLW ymm, ymm, imm8 VPSRLW_YMMqq_YMMqq_IMMbVEX.256.66.0F.WIG 71 /2 ibAVX2
VPSRLW xmm {k}{z}, xmm, imm8 VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512EVEX.128.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW + AVX512VL
VPSRLW xmm {k}{z}, m128, imm8 VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512EVEX.128.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW + AVX512VL
VPSRLW xmm {k}{z}, xmm, xmm VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512EVEX.128.66.0F.WIG D1 /rAVX10.1 or AVX512BW + AVX512VL
VPSRLW xmm {k}{z}, xmm, m128 VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512EVEX.128.66.0F.WIG D1 /rAVX10.1 or AVX512BW + AVX512VL
VPSRLW ymm {k}{z}, ymm, imm8 VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512EVEX.256.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW + AVX512VL
VPSRLW ymm {k}{z}, m256, imm8 VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512EVEX.256.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW + AVX512VL
VPSRLW ymm {k}{z}, ymm, xmm VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512EVEX.256.66.0F.WIG D1 /rAVX10.1 or AVX512BW + AVX512VL
VPSRLW ymm {k}{z}, ymm, m128 VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512EVEX.256.66.0F.WIG D1 /rAVX10.1 or AVX512BW + AVX512VL
VPSRLW zmm {k}{z}, zmm, imm8 VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512EVEX.512.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW
VPSRLW zmm {k}{z}, m512, imm8 VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512EVEX.512.66.0F.WIG 71 /2 ibAVX10.1 or AVX512BW
VPSRLW zmm {k}{z}, zmm, xmm VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512EVEX.512.66.0F.WIG D1 /rAVX10.1 or AVX512BW
VPSRLW zmm {k}{z}, zmm, m128 VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512EVEX.512.66.0F.WIG D1 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128no mask		xmm, xmm, xmm
xmm {k}{z}, xmm, xmmno mask		xmm, xmm, imm8ymm, ymm, m128
ymm {k}{z}, m256, imm8no mask
ymm {k}{z}, ymm, m128no mask		ymm, ymm, xmm
ymm {k}{z}, ymm, xmmno mask		ymm, ymm, imm8xmm {k}{z}, xmm, imm8no mask
ymm {k}{z}, ymm, imm8no mask		xmm {k}{z}, xmm, imm8with a mask, zeroing
ymm {k}{z}, ymm, imm8with a mask, zeroing		xmm {k}{z}, m128, imm8no maskxmm {k}{z}, m128, imm8with a mask, zeroingxmm {k}{z}, xmm, xmmwith a mask, zeroingxmm {k}{z}, xmm, m128with a mask, zeroingymm {k}{z}, m256, imm8with a mask, zeroing
ymm {k}{z}, ymm, m128with a mask, zeroing		ymm {k}{z}, ymm, xmmwith a mask, zeroingzmm {k}{z}, zmm, imm8no maskzmm {k}{z}, zmm, imm8with a mask, zeroingzmm {k}{z}, m512, imm8no mask
zmm {k}{z}, zmm, m128no mask		zmm {k}{z}, m512, imm8with a mask, zeroing
zmm {k}{z}, zmm, m128with a mask, zeroing		zmm {k}{z}, zmm, xmmno maskzmm {k}{z}, zmm, xmmwith a mask, zeroing
Sandy Bridge8 / 1p0152 / 1p0151 / 1p0
Haswell8 / 1p02 / 1p051 / 1p08 / 1p04 / 1p051 / 1p0
Broadwell7 / 1p02 / 1p051 / 1p07 / 1p04 / 1p051 / 1p0
Skylake7 / 0.5p012 / 1p0151 / 0.5p018 / 0.5p014 / 1p0151 / 0.5p01
Skylake-SP7 / 0.5p012 / 1p0151 / 0.5p018 / 0.5p014 / 1p0151 / 0.5p011 / 0.5p011 / 0.5p017 / 0.5p017 / 0.5p012 / 1p0157 / 0.5p018 / 0.5p014 / 1p0151 / 1p01 / 1p08 / 1p08 / 1p04 / 1p054 / 1p05
Ice Lake7 / 0.5p012 / 0.67p0151 / 0.5p018 / 0.5p014 / 1p0151 / 0.5p011 / 0.5p011 / 0.5p017 / 0.5p017 / 0.5p012 / 0.67p0157 / 0.5p018 / 0.5p014 / 1p0151 / 1p01 / 1p08 / 1p08 / 1p04 / 1p054 / 1p05
Alder Lake8 / 0.5p012 / 0.67p0151 / 0.5p019 / 0.5p014 / 1p0151 / 0.5p01
Sapphire Rapids8 / 0.5p012 / 0.67p0151 / 0.5p019 / 0.5p014 / 1p0151 / 0.5p011 / 0.5p013 / 0.5p018 / 0.5p0111 / 0.5p014 / 0.67p01511 / 0.5p0111 / 0.5p016 / 1p0151 / 1p03 / 1p09 / 1p011 / 1p04 / 1p056 / 1p05
Lunar Lake8 / 0.5V0 V12 / 0.5V0 V1 V2 V31 / 0.5V0 V19 / 2.33V0 V14 / 0.5V0 V1 V2 V31 / 0.5V0 V1
Piledriver8 / 1.5FPU1 FPXBR3 / 1FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 1FPU21 / 1FPU21 / 1FPU28 / 2FPU21 / 2FPU21 / 2FPU2
Zen 28 / 1FPU21 / 1FPU21 / 1FPU28 / 1FPU21 / 1FPU21 / 1FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 49 / 1FP1 FP22 / 1FP0 FP11 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP0 FP11 / 0.5FP1 FP21 / 0.5FP0 FP11 / 0.5FP0 FP18 / 0.5FP1 FP28 / 0.5FP1 FP22 / 1FP0 FP19 / 1FP1 FP28 / 0.5FP1 FP22 / 1FP0 FP11 / 0.5FP0 FP11 / 0.5FP0 FP18 / 1FP1 FP28 / 1FP1 FP22 / 1FP0 FP12 / 1FP0 FP1
Jaguar7 / 1FPU0 FPU1 VALU0 VALU12 / 0.5FPU0 FPU1 VALU0 VALU12 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise, by one count: each word is shifted by the count in the low 64 bits of xmm3.VPSRLW xmm, xmm, xmm/m128 VPSRLW ymm, ymm, xmm/m128 VPSRLW xmm {k}{z}, xmm, xmm/m128 VPSRLW ymm {k}{z}, ymm, xmm/m128 VPSRLW zmm {k}{z}, zmm, xmm/m128
VPSRLW: element by elementResult word i comes from word i of xmm2 and the count in xmm3. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.01234567xmm2a11111110k1r0r1r2r3r4r5r7xmm1countxmm3or m128c

Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result word i comes from word i of xmm2 and the count in xmm3. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.

Element-wise: each word of the result comes from the word in the same place in each source.VPSRLW xmm, xmm, imm8 VPSRLW ymm, ymm, imm8 VPSRLW xmm {k}{z}, xmm/m128, imm8 VPSRLW ymm {k}{z}, ymm/m256, imm8 VPSRLW zmm {k}{z}, zmm/m512, imm8
VPSRLW: element by elementResult word i comes from word i of xmm2. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.xmm2or m128a

Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result word i comes from word i of xmm2. Result words 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VPSRLW xmm, xmm, xmm/m128 VPSRLW ymm, ymm, xmm/m128 VPSRLW xmm {k}{z}, xmm, xmm/m128 VPSRLW ymm {k}{z}, ymm, xmm/m128 VPSRLW zmm {k}{z}, zmm, xmm/m128
count = src3.q[0]
for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        zmm1.w[i] = zmm2.w[i] >> count
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

VPSRLW xmm, xmm, imm8 VPSRLW ymm, ymm, imm8 VPSRLW xmm {k}{z}, xmm/m128, imm8 VPSRLW ymm {k}{z}, ymm/m256, imm8 VPSRLW zmm {k}{z}, zmm/m512, imm8
for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        zmm1.w[i] = src2.w[i] >> imm8
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPSRLW xmm, xmm, xmm/m128 VPSRLW ymm, ymm, xmm/m128
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128explicitread
VPSRLW xmm, xmm, imm8 VPSRLW ymm, ymm, imm8
xmm, ymmexplicitwrite
xmm, ymmexplicitread
imm8explicitread
VPSRLW xmm {k}{z}, xmm/m128, imm8 VPSRLW ymm {k}{z}, ymm/m256, imm8 VPSRLW zmm {k}{z}, zmm/m512, imm8
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m128, ymm/m256, zmm/m512explicitread
imm8explicitread
VPSRLW xmm {k}{z}, xmm, xmm/m128 VPSRLW ymm {k}{z}, ymm, xmm/m128 VPSRLW zmm {k}{z}, zmm, xmm/m128
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VPSRLW xmm, xmm, xmm/m128 VPSRLW xmm, xmm, imm8 VPSRLW ymm, ymm, imm8
avx-type-7
VPSRLW ymm, ymm, xmm/m128
avx-type-4
VPSRLW xmm {k}{z}, xmm/m128, imm8 VPSRLW ymm {k}{z}, ymm/m256, imm8 VPSRLW zmm {k}{z}, zmm/m512, imm8
AVX512-E4
VPSRLW xmm {k}{z}, xmm, xmm/m128 VPSRLW ymm {k}{z}, ymm, xmm/m128 VPSRLW zmm {k}{z}, zmm, xmm/m128
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
VPSRLW xmm {k}{z}, m128, imm8 VPSRLW ymm {k}{z}, m256, imm8 VPSRLW zmm {k}{z}, m512, imm8
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSRLW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_srl_epi16 __m128i _mm_srl_epi16(__m128i __a, __m128i __count)

VPSRLW xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_srli_epi16 __m128i _mm_srli_epi16(__m128i __a, int __count)

VPSRLW xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled; with __count a constant

_mm_mask_srl_epi16 __m128i _mm_mask_srl_epi16(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPSRLW xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_mask_srli_epi16 __m128i _mm_mask_srli_epi16(__m128i __W, __mmask8 __U, __m128i __A, int __B)

VPSRLW xmm {k}, xmm, imm8 EVEX.128 -mavx512vl -mavx512bwwith __B a constant

_mm_maskz_srl_epi16 __m128i _mm_maskz_srl_epi16(__mmask8 __U, __m128i __A, __m128i __B)

VPSRLW xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_srli_epi16 __m128i _mm_maskz_srli_epi16(__mmask8 __U, __m128i __A, int __B)

VPSRLW xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vl -mavx512bwwith __B a constant

_mm256_srl_epi16 __m256i _mm256_srl_epi16(__m256i __a, __m128i __count)

VPSRLW ymm, ymm, xmm VEX.256 -mavx2

_mm256_srli_epi16 __m256i _mm256_srli_epi16(__m256i __a, int __count)

VPSRLW ymm, ymm, imm8 VEX.256 -mavx2with __count a constant

_mm256_mask_srl_epi16 __m256i _mm256_mask_srl_epi16(__m256i __W, __mmask16 __U, __m256i __A, __m128i __B)

VPSRLW ymm {k}, ymm, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_mask_srli_epi16 __m256i _mm256_mask_srli_epi16(__m256i __W, __mmask16 __U, __m256i __A, int __B)

VPSRLW ymm {k}, ymm, imm8 EVEX.256 -mavx512vl -mavx512bwwith __B a constant

_mm256_maskz_srl_epi16 __m256i _mm256_maskz_srl_epi16(__mmask16 __U, __m256i __A, __m128i __B)

VPSRLW ymm {k}{z}, ymm, xmm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_srli_epi16 __m256i _mm256_maskz_srli_epi16(__mmask16 __U, __m256i __A, int __B)

VPSRLW ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vl -mavx512bwwith __B a constant

_mm512_srl_epi16 __m512i _mm512_srl_epi16(__m512i __A, __m128i __B)

VPSRLW zmm, zmm, xmm EVEX.512 -mavx512bw

_mm512_srli_epi16 __m512i _mm512_srli_epi16(__m512i __A, unsigned int __B)

VPSRLW zmm, zmm, imm8 EVEX.512 -mavx512bwwith __B a constant

_mm512_mask_srl_epi16 __m512i _mm512_mask_srl_epi16(__m512i __W, __mmask32 __U, __m512i __A, __m128i __B)

VPSRLW zmm {k}, zmm, xmm EVEX.512 -mavx512bw

_mm512_mask_srli_epi16 __m512i _mm512_mask_srli_epi16(__m512i __W, __mmask32 __U, __m512i __A, unsigned int __B)

VPSRLW zmm {k}, zmm, imm8 EVEX.512 -mavx512bwwith __B a constant

_mm512_maskz_srl_epi16 __m512i _mm512_maskz_srl_epi16(__mmask32 __U, __m512i __A, __m128i __B)

VPSRLW zmm {k}{z}, zmm, xmm EVEX.512 -mavx512bw

_mm512_maskz_srli_epi16 __m512i _mm512_maskz_srli_epi16(__mmask32 __U, __m512i __A, int __B)

VPSRLW zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512bwwith __B a constant

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-467 (PSRLW/PSRLD/PSRLQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.