x86-64.net

Instruction

VPSUBB

Subtracts packed bytes, wrapping around on overflow.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPSUBB subtracts the bytes of its second source from those of its first and keeps the low eight bits of each difference, wrapping around with no flags: the VEX and EVEX form of PSUBB, whose page covers negation, constants and other uses. The newer encodings bring what VPADDB lists: a separate destination, memory at any alignment, zeroing above the vector length, AVX for VEX.128 and AVX2 for VEX.256, and EVEX forms that need AVX512BW (or AVX10.1), take a mask bit per byte and cannot broadcast. On Zen 5, vpsubb xmm8, xmm15, xmm0 turned 00h minus 01h into FFh, 80h minus 01h into 7Fh and 7Fh minus FFh into 80h.

Zero and masks

A register minus itself is zero whatever it held: the recorded vpsubb ymm4, ymm4, ymm4 cleared all of ZMM4. AMD’s Zen 5 guide lists VPSUBB of a register from itself, at every width, among the zeroing idioms that take no cycle and do not wait for the old value (Section 2.9.2); Intel’s optimization manual names the xmm and unmasked zmm forms (Section 3.5.1.7). In our builds at -O2, _mm256_sub_epi8(a, a) is VPXOR in GCC 14 and VXORPS in Clang 23.

With -march=x86-64-v4, GCC uses masks for conditional differences of uint8_t arrays in our builds:

  • Absolute differences. b[i] > c[i] ? b[i] - c[i] : c[i] - b[i] is VPCMPUB (as VPCMPNLEUB) into k1, VPSUBB for c - b, and a second VPSUBB under k1 that merges b - c into the bytes where b is greater. Clang subtracts VPMINUB from VPMAXUB instead, at -v3 and -v4.
  • Differences that stop at zero. b[i] > c[i] ? b[i] - c[i] : 0 is the same compare and one VPSUBB with zeroing, where Clang emits VPSUBUSB.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike one cycle and four per cycle on any of pipes FP0 to FP3.

Forms

Every encoding of VPSUBB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPSUBB xmm, xmm, m128 VPSUBB_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG F8 /rAVX
VPSUBB xmm, xmm, xmm VPSUBB_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG F8 /rAVX
VPSUBB ymm, ymm, m256 VPSUBB_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG F8 /rAVX2
VPSUBB ymm, ymm, ymm VPSUBB_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG F8 /rAVX2
VPSUBB xmm {k}{z}, xmm, xmm VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512EVEX.128.66.0F.WIG F8 /rAVX10.1 or AVX512BW + AVX512VL
VPSUBB xmm {k}{z}, xmm, m128 VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512EVEX.128.66.0F.WIG F8 /rAVX10.1 or AVX512BW + AVX512VL
VPSUBB ymm {k}{z}, ymm, ymm VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512EVEX.256.66.0F.WIG F8 /rAVX10.1 or AVX512BW + AVX512VL
VPSUBB ymm {k}{z}, ymm, m256 VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512EVEX.256.66.0F.WIG F8 /rAVX10.1 or AVX512BW + AVX512VL
VPSUBB zmm {k}{z}, zmm, zmm VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512EVEX.512.66.0F.WIG F8 /rAVX10.1 or AVX512BW
VPSUBB zmm {k}{z}, zmm, m512 VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512EVEX.512.66.0F.WIG F8 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128no mask		xmm, xmm, xmm
xmm {k}{z}, xmm, xmmno mask
ymm {k}{z}, ymm, ymmno mask		ymm, ymm, m256
ymm {k}{z}, ymm, m256no mask		ymm, ymm, ymmxmm {k}{z}, xmm, xmmwith a mask, zeroing
ymm {k}{z}, ymm, ymmwith a mask, zeroing		xmm {k}{z}, xmm, m128with a mask, zeroingymm {k}{z}, ymm, m256with a mask, zeroingzmm {k}{z}, zmm, zmmno maskzmm {k}{z}, zmm, zmmwith a mask, zeroingzmm {k}{z}, zmm, m512no maskzmm {k}{z}, zmm, m512with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p0151 / 0.33p0158 / 0.5p0151 / 0.33p015
Skylake-SP, Ice Lake7 / 0.5p0151 / 0.33p0158 / 0.5p0151 / 0.33p0151 / 0.33p0157 / 0.5p0158 / 0.5p0151 / 0.33p0151 / 0.33p0158 / 0.5p0158 / 0.5p015
Alder Lake8 / 0.33p0151 / 0.33p0159 / 0.33p0151 / 0.33p015
Sapphire Rapids8 / 0.33p0151 / 0.33p0159 / 0.33p0151 / 0.33p0153 / 0.33p01511 / 0.33p01511 / 0.33p0151 / 0.5p053 / 0.5p059 / 0.5p0511 / 0.5p05
Lunar Lake7 / 2V0 V1 V2 V31 / 0.25V0 V1 V2 V38 / 2.33V0 V1 V2 V31 / 0.25V0 V1 V2 V3
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP3
Zen 48 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.
VPSUBB: element by elementResult byte i comes from byte i of xmm2 and xmm3. Result bytes 7 to 0: a7-b7, unchanged (bit 6 of k1 is 0), a5-b5, a4-b4, a3-b3, a2-b2, a1-b1, a0-b0.…01234567xmm2a11111110k1…a0-b0a1-b1a2-b2a3-b3a4-b4a5-b5a7-b7xmm1…01234567xmm3or m128b

Shown: bytes 7 to 0. Every byte works alike: 16, 32 and 64 bytes in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result byte i comes from byte i of xmm2 and xmm3. Result bytes 7 to 0: a7-b7, unchanged (bit 6 of k1 is 0), a5-b5, a4-b4, a3-b3, a2-b2, a1-b1, a0-b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:  # 1 without a write mask
        zmm1.b[i] = zmm2.b[i] - src3.b[i]
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPSUBB xmm, xmm, xmm/m128 VPSUBB ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPSUBB xmm {k}{z}, xmm, xmm/m128 VPSUBB ymm {k}{z}, ymm, ymm/m256 VPSUBB zmm {k}{z}, zmm, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSUBB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_sub_epi8 __m128i _mm_sub_epi8(__m128i __a, __m128i __b)

VPSUBB xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_sub_epi8 __m128i _mm_mask_sub_epi8(__m128i __W, __mmask16 __U, __m128i __A, __m128i __B)

VPSUBB xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_sub_epi8 __m128i _mm_maskz_sub_epi8(__mmask16 __U, __m128i __A, __m128i __B)

VPSUBB xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_sub_epi8 __m256i _mm256_sub_epi8(__m256i __a, __m256i __b)

VPSUBB ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_sub_epi8 __m256i _mm256_mask_sub_epi8(__m256i __W, __mmask32 __U, __m256i __A, __m256i __B)

VPSUBB ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_sub_epi8 __m256i _mm256_maskz_sub_epi8(__mmask32 __U, __m256i __A, __m256i __B)

VPSUBB ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_sub_epi8 __m512i _mm512_sub_epi8(__m512i __A, __m512i __B)

VPSUBB zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_sub_epi8 __m512i _mm512_mask_sub_epi8(__m512i __W, __mmask64 __U, __m512i __A, __m512i __B)

VPSUBB zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_sub_epi8 __m512i _mm512_maskz_sub_epi8(__mmask64 __U, __m512i __A, __m512i __B)

VPSUBB zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-479 (PSUBB/PSUBW/PSUBD)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  9. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.