VPSUBQ

VPSUBQ subtracts the quadwords of its second source from those of its first and keeps the low 64 bits of each difference, wrapping around with no flags: on Zen 5, vpsubq xmm12, xmm6, [mem] turned 7FFFFFFFFFFFFFFFh minus FFFFFFFFFFFFFFFFh into 8000000000000000h. It is the VEX and EVEX form of SSE2’s PSUBQ. The VPSUBD page covers what subtraction adds to the encodings, the operand order that decides which side may come from memory, negation from zero and the zeroing idiom, and VPADDQ the quadword width: 256 bits with AVX2, 512 and a write mask per quadword with AVX512F, and a broadcast quadword ({1to8} for zmm).

Quadwords in compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 use VPSUBQ for int64_t and pointer differences, a[i] = b[i] - c[i] with c from memory, and for a few things AVX2 lacks:

• Absolute value. There is no 64-bit VPABSQ before AVX-512. For b[i] < 0 ? -b[i] : b[i], GCC compares with zero by VPCMPGTQ, flips the bits with VPXOR and subtracts the compare’s -1, and Clang subtracts from zero and picks by the sign bit with VBLENDVPD. With -march=x86-64-v4, both use AVX512F’s VPABSQ.
• Adding one. Subtracting -1 adds one, and an all-ones register costs no constant: in the shorter of its two vector loops for a[i] = b[i] + 1 over a count n, Clang makes ones with VPCMPEQD and subtracts them. On Zen 5, vpsubq zmm14{k2}, zmm8, qword bcst [mem] with -1 in memory turned 10h into 11h and 7FFFFFFFFFFFFFFFh into 8000000000000000h in the elements K2 selected.

With -march=x86-64-v4, both compilers fold _mm512_sub_epi64(x, _mm512_set1_epi64(*p)) into vpsubq zmm0, zmm0, qword ptr [rdi]{1to8}. A constant is added instead: x - 1000 becomes VPADDQ of -1000, from a broadcast pool entry in Clang and from RAX through VPBROADCASTQ in GCC.

AMD’s latency spreadsheet for Zen 5 gives VPSUBQ one cycle and four per cycle, and its guide lists VPSUBQ of a register from itself among the zeroing idioms (Section 2.9.2). Zen 5’s 10 recorded cases cover every form, merging, zeroing and with a broadcast quadword.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = zmm2.q[i] - src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPSUBQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD

All 253 AVX instructions

More AVX2 instructions

• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLVW
• VPSLLW
• VPSRAD
• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW

All 686 AVX10.1 instructions