VPTERNLOGD

VPTERNLOGD computes any bitwise function of three inputs, and its immediate is that function’s truth table. For each bit position, the bits of the first operand (also the destination), the second and the third form a number from 0 to 7, and that bit of the immediate is the result. One instruction therefore replaces any combination of AND, OR, XOR and NOT on three vectors.

To find the immediate, evaluate the wanted expression with F0h, CCh and AAh standing for the first, second and third operand:

Compilers lean on it in three ways:

• All ones. EVEX compares write mask registers, not vectors, so the AVX2 idiom VPCMPEQD of a register with itself cannot fill a ZMM register. Instead GCC 14 and Clang 23 at -O2 emit VPTERNLOGD with FFh, as Intel’s optimization manual does; GCC first clears the register with VPXOR.
• NOT. There is no vector NOT; both compilers use VPTERNLOG with the register in all three operands, GCC with the immediate 55h and Clang with 33h.
• Select and three-way XOR, which take two or three instructions otherwise.

The destination is also the first input, so a compiler copies an input it still needs before the instruction overwrites it. Changing the order of the operands changes the immediate, which lets a compiler choose the input to overwrite: for the same select, GCC used E4h and Clang CAh.

The D in the name matters only for masking, which works per doubleword, and for the size of a broadcast element. Without either, VPTERNLOGQ gives the same result, and Clang emits it for logic intrinsics that name no element size, such as _mm512_xor_si512.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm1.d[i]
        b = zmm2.d[i]
        c = src3.d[i]
        zmm1.d[i] = ternlog(imm8, a, b, c)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTERNLOGD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRAQ
• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD

All 686 AVX10.1 instructions