VPTERNLOGQ

VPTERNLOGQ computes a bitwise function of three inputs whose truth table is its immediate, exactly as VPTERNLOGD does; that page explains how to read and build the immediate. The two differ only where elements matter: VPTERNLOGQ applies a write mask per quadword and broadcasts a quadword from memory, so it is the one to use with a mask from a 64-bit compare such as VPCMPQ, or with a 64-bit constant in memory. Without either, both give the same bits, and the compilers pick freely: GCC 14 and Clang 23 at -O2 fill a vector of uint64_t with ones using VPTERNLOGD and the immediate FFh.

Three-input steps in 64-bit algorithms#

Hash functions built on 64-bit words, such as SHA-512 and SHA-3, are full of three-input logic. With F0h, CCh and AAh standing for the first, second and third operand, the immediate is the expression evaluated on them:

On uint64_t vector types with -march=x86-64-v4, Clang 23 compiles a ^ (~b & c) to one VPTERNLOGQ with D2h, and GCC 14 to one with B4h, having put the operands in the order a, c, b. Both find 96h for the three-way XOR and a single instruction for Ch. For the majority, whether written as (a & b) ^ (a & c) ^ (b & c), with ORs, or as (a & b) | (c & (a | b)), both emit two VPTERNLOGQ instead of one with E8h; the intrinsic _mm512_ternarylogic_epi64(a, b, c, 0xE8) gives the single instruction.

Recorded on Zen 5#

The cases recorded on Zen 5 include E8h with a broadcast quadword and zeroing: each selected quadword became the majority of its three inputs, and the others zero. Immediate 0Fh, NOT of the first operand, inverted only the quadwords whose mask bits were set.

AMD’s Zen 5 guide lists VPTERNLOGQ as one macro-op with a latency of one cycle and a throughput of four per cycle, at every width.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm1.q[i]
        b = zmm2.q[i]
        c = src3.q[i]
        zmm1.q[i] = ternlog(imm8, a, b, c)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTERNLOGQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRAVD
• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS

All 686 AVX10.1 instructions