VPTEST

VPTEST is PTEST in a VEX encoding: it ANDs two vectors without keeping the result, sets ZF when the AND is all zeros and CF when the second operand ANDed with the inverted first is all zeros, and clears OF, SF, AF and PF. The PTEST page explains the two answers and the intrinsics that read them. The VEX.256 form is what this page adds, a test of 32 bytes at once; the VEX.128 form is PTEST with a memory operand at any address. On Zen 5, vptest ymm8, ymm15 on two unrelated values changed RFLAGS from A97h to 202h: CF, PF, AF, SF and OF were cleared, and ZF, already clear, stayed so.

In compiled code#

At -O2 with -march=x86-64-v3, GCC 14 and Clang 23 compile memcmp(p, q, 32) == 0 to a load, VPXOR with the other block in memory, vptest ymm0, ymm0 and SETE, and _mm256_testz_si256(a, a) and _mm256_testc_si256(a, b) to VPTEST and SETE or SETB. For 64 bytes the two differ. Clang ORs the two XOR results with VPOR and tests once; GCC tests each half and branches after the first. With -march=x86-64-v4, Clang 23 keeps VPTEST and merges the second half with VPTERNLOGQ, while GCC 14 compares the whole 64 bytes with VPCMPEQD into a mask register and tests that with KORTESTW.

AVX-512 has no flag-setting test of a ZMM register: VPTEST stops at 256 bits, and VPTESTMD and its kin write a mask register instead. VTESTPS and VTESTPD are the VEX tests of sign bits only.

AMD’s latency spreadsheet for Zen 5 lists VPTEST as two macro-ops, on pipes 1 or 2 and 4 or 5, two per cycle. Zen 5’s 4 recorded cases cover the register and memory forms at both widths.

In the optimization guide

What the optimization guide says about VPTEST, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit vector tests take 7 cycles from the vectors to the flags.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

zf = ymm1.read() & src2.read() == 0
cf = ~ymm1.read() & src2.read() == 0
of = sf = af = pf = 0

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTEST, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD

All 253 AVX instructions