VPTESTMB

VPTESTMB ANDs each pair of bytes and sets a bit of the destination mask register where the AND has any bit set, one bit per byte: 16, 32 or 64 of them. It is the byte form of VPTESTMD, whose page explains the family and the common tests, and needs AVX512BW; VPTESTNMB sets the bits where the AND is zero. Byte elements bring one difference: the memory operand cannot be a broadcast, so a constant to test against is a whole vector.

Recorded on Zen 5#

In its one recorded case, vptestmb k4{k2}, xmm14, xmm8, the ANDs of the 16 byte pairs were nonzero in bytes 3 to 7, 9 to 12 and 14, which is 5EF8h; bytes 13 and 15 paired 00h with 80h and 10h with 01h, which share no bit. K2 held F2C9h in its low 16 bits, and K4 received the AND of the two, 52C8h, with every bit above 15 cleared.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile _mm512_test_epi8_mask to VPTESTMB. They part on the rest:

• Masked test. GCC keeps _mm512_mask_test_epi8_mask as vptestmb k0{k1}; Clang tests unmasked and ANDs the 64-bit result in a general register.
• Nonzero bytes. For _mm512_cmpneq_epi8_mask(a, zero) Clang tests a with itself; GCC compares with a zeroed register using VPCMPB.
• A bit of every byte. Against _mm512_set1_epi8(0x20), GCC broadcasts the byte with VPBROADCASTB and Clang loads a 64-byte constant. For 80h, the sign bits, Clang uses VPMOVB2M instead.
• Selecting bytes. d[i] = (s[i] & t[i]) ? s[i] : 0 over uint8_t arrays is VPTESTMB and a zero-masked VMOVDQU8 in Clang, on YMM registers, and VPANDQ, VPCMPB and VMOVDQU8 in GCC.

AMD’s Zen 5 latency spreadsheet gives VPTESTMB 3, 4 and 6 cycles for XMM, YMM and ZMM sources, two per cycle on pipes FP1 and FP2, as VPTESTMD; the memory forms are two macro-ops.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    a = zmm2.b[i]
    b = src3.b[i]
    k1[i] = k2[i] and a & b != 0
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTESTMB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRAVQ
• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD

All 686 AVX10.1 instructions