VPTESTMD

VPTESTMD ANDs each pair of doublewords and sets a mask bit where the AND has any bit set; VPTESTNMD sets it where the AND is zero. Where PTEST folds a whole register into ZF and CF, these keep one answer per element in a mask register, with the masking of the compares: an element the write mask leaves out gets 0, and the bits above the element count are cleared. The doubleword and quadword forms are AVX-512F; VPTESTMB and VPTESTMW need AVX512BW.

Three common tests#

• Nonzero elements. VPTESTMD of a register with itself marks the nonzero elements and VPTESTNMD the zero ones, a compare with zero that needs no zeroed register. GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 both compile _mm512_cmpeq_epi32_mask(a, zero) to vptestnmd k0, zmm0, zmm0; for not equal, Clang emits VPTESTMD of a with itself, while GCC clears a register and uses VPCMPD with predicate 4. Clang also vectorizes o[i] = a[i] ? 7 : o[i] with VPTESTNMD and a VPBLENDMD.
• Flag bits. Against a broadcast constant, the test picks one bit or a set of bits out of every element; Clang folds the constant into a {1to16} operand. For (a & b) != 0 on vectors of int, Clang emits one VPTESTMD, GCC a VPANDD and a VPCMPD.
• Any element at all. VPTESTMD and then KORTESTW of the mask with itself sets ZF when no element passed, which a branch can test. Intel’s optimization manual does this in its histogram loop (Section 17.16.1, Example 17-24): VPTESTMD of the VPCONFLICTD result with itself and KORTESTW skip the merging of repeated indices when there are none.

The same manual makes the bitmask of a sparse matrix with VPTESTMB, a bit per nonzero byte, and packs the nonzero bytes with VPCOMPRESS (Section 20.18). AMD’s Zen 5 guide lists VPTESTMD with the latencies of VPCMPD, 3, 4 and 6 cycles for XMM, YMM and ZMM.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = zmm2.d[i]
    b = src3.d[i]
    k1[i] = k2[i] and a & b != 0
# m32bcst: src3.d[i] is the m32 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTESTMD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRAVW
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS

All 686 AVX10.1 instructions