VPTESTMQ

VPTESTMQ ANDs each pair of quadwords and sets a bit of the destination mask register where the AND has any bit set, one bit per quadword: 2, 4 or 8 of them, with every higher bit of the mask cleared. It is the quadword form of VPTESTMD, whose page explains the family and the common tests, and VPTESTNMQ sets the bits where the AND is zero. Unlike the byte and word forms, its memory operand may be one quadword broadcast to all elements, which suits a 64-bit flag constant.

Recorded on Zen 5#

• Bits must overlap. In vptestmq k7{k6}, zmm9, zmmword ptr [mem] quadword 3 paired 8000000000000000h with 7FFFFFFFFFFFFFFFh, which share no bit, and got 0; quadword 2, 8 against 8, got 1. The ANDs were nonzero in elements 0, 2 and 7, 85h, and K6’s low byte A4h left 84h in K7.
• The write mask clears, it does not keep: vptestmq k5{k7}, zmm24, zmm3 found 7Bh, and K5, which held 606489354489D5E1h, received 7Bh AND E3h, 63h, and nothing else.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile _mm512_test_epi64_mask to VPTESTMQ. The constants show the difference between them:

• A flag bit. Against _mm512_set1_epi64(0x20), Clang tests with a {1to8} broadcast from memory; GCC broadcasts the constant into a register with VPBROADCASTQ first.
• The sign bit. Against 1ULL << 63 GCC does the same, while Clang replaces the test with VPMOVQ2M, which copies each sign bit to the mask.
• A select. d[i] = (s[i] & t[i]) ? s[i] : 0 over uint64_t arrays is VPTESTMQ and a zero-masked VMOVDQA64 in Clang, on YMM registers, and VPANDQ, VPCMPQ and VMOVDQA64 in GCC.

AMD’s Zen 5 latency spreadsheet gives VPTESTMQ 3, 4 and 6 cycles for XMM, YMM and ZMM sources, two per cycle on pipes FP1 and FP2, as VPTESTMD; the memory forms are two macro-ops. The 6 recorded cases cover the register and memory forms at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    a = zmm2.q[i]
    b = src3.q[i]
    k1[i] = k2[i] and a & b != 0
# m64bcst: src3.q[i] is the m64 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTESTMQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD

All 686 AVX10.1 instructions