VPTESTMW

VPTESTMW ANDs each pair of words and sets a bit of the destination mask where the AND has any bit set, one bit per word: 8, 16 or 32 of them. It is the word form of VPTESTMD, whose page explains the family and the common tests, and of VPTESTMB; VPTESTNMW sets the bits where the AND is zero. It needs AVX512BW and has no broadcast form.

Recorded on Zen 5#

• Any shared bit. In vptestmw k1, ymm1, ymm2, 8000h against FFFFh and 000Fh against 0001h set their bits, and 8000h against 7FFFh, 0010h against 0001h and 0 against 0 did not, giving BE15h.
• The write mask. vptestmw k5{k3}, xmm24, xmmword ptr [mem] set the bits of four of the six words K3 selected, E1h, and none outside; the words left out were 8000h against 7FFFh and 0 against 1.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_test_epi16_mask to VPTESTMW. They part on the rest:

• Selecting words. For o[i] = (a[i] & b[i]) ? a[i] : 0 over uint16_t arrays, Clang tests a[i] against b[i] in memory, on YMM registers; GCC ANDs them with VPANDQ and compares the result with zero, using VPCMPW with predicate 4. Both store through a zero-masked VMOVDQU16.
• Nonzero words. _mm512_cmpneq_epi16_mask(a, zero) is vptestmw k0, zmm0, zmm0 in Clang and VPCMPW against a zeroed register in GCC.
• Masked test. GCC keeps _mm512_mask_test_epi16_mask as vptestmw k0{k1}; Clang tests unmasked and ANDs in EAX.

AMD’s Zen 5 latency spreadsheet gives VPTESTMW 3, 4 and 6 cycles for XMM, YMM and ZMM, one macro-op on FP1 or FP2 and two with a memory source, as VPTESTMB.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    a = zmm2.w[i]
    b = src3.w[i]
    k1[i] = k2[i] and a & b != 0
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTESTMW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS

All 686 AVX10.1 instructions