VPTESTNMB

VPTESTNMB sets bit i of its destination mask where bytes i of its two sources share no 1 bit, that is where their AND is zero, for 16, 32 or 64 bytes. It is the byte form of VPTESTNMD, whose page explains the tests and the write mask, which leaves 0 in the elements it excludes, and the complement of VPTESTMB. It needs AVX512BW and, unlike the doubleword form, takes no broadcast operand.

Recorded on Zen 5#

• Shared bits only. In vptestnmb k6, ymm17, ymm30, 80h against 7Fh, 10h against 01h and 00h against anything set their bits, while FFh against 01h and 80h against FFh did not; the 32 results gave 420F5083h.
• A register with itself marks its zero bytes: in vptestnmb k3{k2}, xmm9, xmm9 none of the nine bytes K2 selected was zero, and the result was 0.
• The write mask. In vptestnmb k7{k6}, zmm7, zmm12 no bit was set outside K6.

Finding a zero byte#

The test of a register with itself is the vector form of a string’s end: with GCC 14 and Clang 23 at -O2 and -march=x86-64-v4, a loop that looks for the first zero byte, 64 bytes at a time with _mm512_cmpeq_epi8_mask against zero, is vptestnmb k0, zmm0, zmm0 and KORTESTQ in Clang; GCC compares with VPCMPEQB against a zeroed register. _mm512_testn_epi8_mask(a, a) is VPTESTNMB in both.

For o[i] = (a[i] & b[i]) == 0 ? a[i] : 0 over uint8_t arrays, Clang tests a[i] against b[i] in memory, on YMM registers, and GCC first ANDs them with VPANDQ and tests the result with itself; both finish with a zero-masked VMOVDQU8. GCC keeps _mm512_mask_testn_epi8_mask as a masked VPTESTNMB, while Clang tests unmasked and ANDs the mask in RAX.

AMD’s Zen 5 latency spreadsheet gives VPTESTNMB 3, 4 and 6 cycles for XMM, YMM and ZMM, one macro-op on FP1 or FP2 and two with a memory source.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    a = zmm2.b[i]
    b = src3.b[i]
    k1[i] = k2[i] and a & b == 0
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTESTNMB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD

All 686 AVX10.1 instructions