VPTESTNMD

VPTESTNMD sets bit i of its destination mask when doublewords i of its two sources have no 1 bit in the same position, that is when their AND is zero. It is the complement of VPTESTMD, whose page covers the tests both share; the masking is that of the compares: an element the write mask leaves out gets 0, not its old bit, and the mask bits above the element count are cleared. In a ymm case recorded on Zen 5, the only pair whose AND was zero was 80000000h and 1, element 4, and the result was 10h. Intel’s manual titles the instruction “Logical NAND and Set”, but no bitwise NAND is computed: the bit tests the AND for zero.

Testing for clear bits#

• Zero elements. VPTESTNMD of a register with itself marks the zero elements, which is how both compilers compile a compare with zero (see VPTESTMD).
• Flags all clear. Against a constant, the bit says that none of the constant’s bits is set in the element. Clang 23 at -O2 with -march=x86-64-v4 vectorizes if ((f[i] & 0x30) == 0) o[i] = 0; with VPTESTNMD against a register of 30h and a masked VMOVDQU32 store; GCC 14 keeps the loop scalar. For _mm512_testn_epi32_mask(a, _mm512_set1_epi32(1)), the even elements, Clang folds the constant into a {1to16} operand, GCC broadcasts it into a register first.
• A vector result. For (a & b) == 0 on vectors of int, Clang emits one VPTESTNMD and turns the mask into elements of all ones or zero with VPMOVM2D; GCC emits VPANDD, VPTESTNMD of the result with itself and VPMOVM2D.

Under a write mask#

Since a masked-off element gives 0, vptestnmd k1{k2}, a, b is k2 AND the test. GCC compiles _mm512_mask_testn_epi32_mask to exactly that; Clang emits the unmasked instruction, moves the mask to a general-purpose register with KMOVD and ANDs it there. To branch on any zero element, both follow VPTESTNMD of a register with itself by KORTESTW, which clears ZF when a bit is set.

AMD’s Zen 5 guide lists VPTESTNMD with the latencies of VPTESTMD, 3, 4 and 6 cycles for xmm, ymm and zmm. VPTESTNMQ tests quadwords; VPTESTNMB and VPTESTNMW, bytes and words, need AVX512BW and take no broadcast.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    a = zmm2.d[i]
    b = src3.d[i]
    k1[i] = k2[i] and a & b == 0
# m32bcst: src3.d[i] is the m32 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTESTNMD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS

All 686 AVX10.1 instructions