VPTESTNMQ

VPTESTNMQ sets bit i of its destination mask when quadwords i of its two sources AND to zero: 2, 4 or 8 bits for the XMM, YMM and ZMM forms. It is the quadword form of VPTESTNMD, whose page covers the masking it shares with the compares, and the complement of VPTESTMQ. It came with AVX512F and takes a 64-bit broadcast. A register tested against itself marks the zero quadwords; against a constant, the elements in which those bits are all clear.

Recorded on Zen 5#

• Two zero ANDs. vptestnmq k6{k3}, zmm24, zmm3 gave 42h: 8000000000000000h against 1 and 0 against 8000000000000000h AND to zero, while F against 1 and 8000000000000000h against itself do not. The register and memory forms gave the same 42h, and the other 56 bits of K6 and K5 were cleared.
• Nothing selected. In vptestnmq k5{k1}, xmm17, xmm30 the low two bits of K1 were clear, and K5 became 0.

In compiled code#

At -O2 with -march=x86-64-v4, (q[i] & 7) == 0 ? q[i] : 0 over int64_t is VPTESTNMQ and a zero-masked move in GCC 14 and Clang 23. Clang tests q[i] against a vector of sevens; GCC first ANDs with VPANDQ and tests the result against itself. A test whether a whole vector is zero, written as _mm512_testn_epi64_mask(a, a) == 0xff, is VPTESTNMQ, KMOVB and a compare of AL with FFh in GCC, while Clang turns it into VPTESTMD and KORTESTW.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2 and 3, 4 and 6 cycles for XMM, YMM and ZMM sources, with a second macro-op for a memory operand.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    a = zmm2.q[i]
    b = src3.q[i]
    k1[i] = k2[i] and a & b == 0
# m64bcst: src3.q[i] is the m64 for every i
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTESTNMQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRLVD
• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH

All 686 AVX10.1 instructions