VPTESTNMW

VPTESTNMW sets bit i of its destination mask when words i of its two sources have no 1 bit in common, that is when their AND is zero: 8, 16 or 32 bits for the XMM, YMM and ZMM forms. It is the word form of VPTESTNMD, whose page covers the masking it shares with the compares, and the complement of VPTESTMW. Like VPTESTNMB it needs AVX512BW. With one register named twice, it marks the words that are zero.

Recorded on Zen 5#

• AND, not equality. {evex} vptestnmw k7, ymm24, ymm3 gave 7A84h: 8000h against 1, 0 against 8000h, 10h against 1 and 8000h against 7FFFh all count as zero, while FFFFh against FFFFh, 7FFFh against 1 and 8000h against 8000h do not.
• Under a write mask. vptestnmw k5{k2}, zmm1, zmm2 gave 78841281h, the bits of the AND test that K2 also selects; every other bit of K5, the upper 32 included, became 0.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile h[i] == 0 ? c[i] : h[i] over int16_t to VPTESTNMW of one register with itself and a masked VMOVDQU16 load of c[i]. For (h[i] & c[i]) == 0 ? 1 : h[i], Clang tests the two arrays with VPTESTNMW, one from memory, while GCC computes the AND with VPANDQ, compares it with zero using VPCMPW and blends with VPBLENDMW. _mm512_testn_epi16_mask is one VPTESTNMW and a KMOVD.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2 and 3, 4 and 6 cycles for XMM, YMM and ZMM sources, with a second macro-op for a memory operand.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    a = zmm2.w[i]
    b = src3.w[i]
    k1[i] = k2[i] and a & b == 0
# the other bits of k1 are cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPTESTNMW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSRLVQ
• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH

All 686 AVX10.1 instructions