VPUNPCKHBW

VPUNPCKHBW interleaves the high bytes of its two sources, a byte of the first, a byte of the second, and so on: the high-half partner of VPUNPCKLBW, whose page covers what the VEX and EVEX encodings bring and the lanes that make interleaving whole registers awkward. It is the newer form of SSE2’s PUNPCKHBW. Above 128 bits each lane takes its own high eight bytes: on Zen 5, vpunpckhbw ymm0, ymm13, ymm9 filled bytes 0 to 15 of the result from bytes 8 to 15 of each source, beginning with 1Dh and 01h from byte 8, and bytes 16 to 31 from bytes 24 to 31. Bytes 0 to 7 and 16 to 23 went to VPUNPCKLBW’s share.

Multiplying bytes#

There is no byte multiply, and GCC 14 builds one from word products. At -O2 with -march=x86-64-v3, it compiles a[i] = b[i] * c[i] over uint8_t by unpacking each source with itself, VPUNPCKLBW and VPUNPCKHBW of the same register, so that every word holds a byte twice. VPMULLW multiplies the words, and the low byte of each product is right, since it depends only on the low bytes of the factors. VPSHUFB gathers those bytes and VPBLENDD joins the two halves. Unpacking and gathering both stay in their lanes, so the bytes come back in order without a lane-crossing repair. With -march=x86-64-v4, GCC does the same on zmm registers and gathers with VPERMT2W. Clang 23 unpacks nothing: it multiplies the even bytes in place with VPMULLW and the odd ones with VPMADDUBSW, and merges them with a mask and a shift.

Widening alone needs no unpack since SSE4.1: int8_t to int16_t is VPMOVSXBW in both compilers. The unpack against zero remains for the intrinsics, _mm256_unpackhi_epi8(a, _mm256_setzero_si256()) becoming VPXOR and VPUNPCKHBW.

AMD’s latency spreadsheet for Zen 5 gives VPUNPCKHBW one cycle, four per cycle at every width. Zen 5’s 10 recorded cases cover every form, merging and zeroing included.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    j = i - i % 16 + i % 16 // 2 + 8  # in the lane of i
    if k1[i]:                         # 1 without a write mask
        if i % 2 == 0:
            zmm1.b[i] = zmm2.b[j]
        else:
            zmm1.b[i] = src3.b[j]
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPUNPCKHBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS

All 253 AVX instructions

More AVX2 instructions

• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSRLVW
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD

All 686 AVX10.1 instructions