x86-64.net

Instruction

VPUNPCKHDQ

Interleaves the high doublewords of each 128-bit lane of two sources.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPUNPCKHDQ interleaves doublewords 2 and 3 of each 128-bit lane of its two sources: the VEX and EVEX form of PUNPCKHDQ, whose page covers the high-half jobs at the baseline. VPUNPCKLDQ gives what the newer encodings add (three operands, AVX2 for ymm, AVX512F or AVX10.1 for the EVEX forms with masks and a broadcast doubleword) and what compilers do with the pair. With the same register twice it doubles the high elements of each lane: on Zen 5, vpunpckhdq ymm4, ymm4, ymm4 wrote 05F8EBDEh, 05F8EBDEh, 392C1F12h, 392C1F12h in the low lane and D5C8BBAEh and 09FCEFE2h twice each in the high one. In vpunpckhdq zmm5{k2}, zmm5, dword bcst [mem], the broadcast 763B00C5h filled the odd elements k2 selects, 3, 7, 9, 13 and 15.

In compiled code

In our builds at -O2, GCC 14 compiles _mm256_unpackhi_epi32(a, a) to VPUNPCKHDQ at -march=x86-64-v3 and -v4, and Clang 23 to VSHUFPS with FAh, which moves the same bits. An eight-register transpose spelled with _mm256_unpacklo_epi32, its kin and the quadword unpacks transposes a 4x4 block of doublewords in each lane at once; GCC keeps the integer unpacks, while Clang writes all of them as VUNPCKLPS, VUNPCKHPS, VUNPCKLPD and VUNPCKHPD.

Intel’s optimization manual uses that lane behaviour on purpose to transpose BF16 matrices for AMX: masked VBROADCASTI32X4 loads give the four lanes of a register rows 8 apart, and VPUNPCKLWD, VPUNPCKHWD, the doubleword unpacks and then the quadword ones transpose four 8x8 blocks of words at once (Section 20.16.1, Example 20-26). AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike one cycle and four per cycle.

Forms

Every encoding of VPUNPCKHDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPUNPCKHDQ xmm, xmm, m128 VPUNPCKHDQ_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG 6A /rAVX
VPUNPCKHDQ xmm, xmm, xmm VPUNPCKHDQ_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG 6A /rAVX
VPUNPCKHDQ ymm, ymm, m256 VPUNPCKHDQ_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG 6A /rAVX2
VPUNPCKHDQ ymm, ymm, ymm VPUNPCKHDQ_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG 6A /rAVX2
VPUNPCKHDQ zmm {k}{z}, zmm, zmm VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512EVEX.512.66.0F.W0 6A /rAVX10.1 or AVX512F
VPUNPCKHDQ zmm {k}{z}, zmm, m512/m32bcst VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512EVEX.512.66.0F.W0 6A /rAVX10.1 or AVX512F
VPUNPCKHDQ xmm {k}{z}, xmm, xmm VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512EVEX.128.66.0F.W0 6A /rAVX10.1 or AVX512F + AVX512VL
VPUNPCKHDQ xmm {k}{z}, xmm, m128/m32bcst VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512EVEX.128.66.0F.W0 6A /rAVX10.1 or AVX512F + AVX512VL
VPUNPCKHDQ ymm {k}{z}, ymm, ymm VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512EVEX.256.66.0F.W0 6A /rAVX10.1 or AVX512F + AVX512VL
VPUNPCKHDQ ymm {k}{z}, ymm, m256/m32bcst VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512EVEX.256.66.0F.W0 6A /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128/m32bcst		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm		ymm, ymm, m256
ymm {k}{z}, ymm, m256/m32bcst		ymm, ymm, ymmzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m32bcst
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p58 / 1p5
Ice Lake7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p151 / 1p58 / 1p5
Alder Lake8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p15
Sapphire Rapids8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p151 / 1p59 / 1p5
Lunar Lake8 / 0.5V2 V31 / 0.5V2 V39 / 0.5V2 V31 / 0.5V2 V3
Piledriver7 / 1.5FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP21 / 1FP1 FP28 / 1FP1 FP2
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the high doublewords of both sources alternate in the result, those of xmm2 in the even places.
VPUNPCKHDQ: high halves interleavedResult doublewords 3 to 0: b3, unchanged (bit 2 of k1 is 0), b2, a2.0123xmm2a1110k1a2b2b3xmm10123xmm3or m128b

The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of xmm3.

Result doublewords 3 to 0: b3, unchanged (bit 2 of k1 is 0), b2, a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    j = i - i % 4 + i % 4 // 2 + 2  # in the lane of i
    if k1[i]:                       # 1 without a write mask
        if i % 2 == 0:
            zmm1.d[i] = zmm2.d[j]
        else:
            zmm1.d[i] = src3.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPUNPCKHDQ xmm, xmm, xmm/m128 VPUNPCKHDQ ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPUNPCKHDQ xmm {k}{z}, xmm, xmm/m128/m32bcst VPUNPCKHDQ ymm {k}{z}, ymm, ymm/m256/m32bcst VPUNPCKHDQ zmm {k}{z}, zmm, zmm/m512/m32bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPUNPCKHDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_unpackhi_epi32 __m128i _mm_unpackhi_epi32(__m128i __a, __m128i __b)

VPUNPCKHDQ xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_unpackhi_epi32 __m128i _mm_mask_unpackhi_epi32(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPUNPCKHDQ xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_unpackhi_epi32 __m128i _mm_maskz_unpackhi_epi32(__mmask8 __U, __m128i __A, __m128i __B)

VPUNPCKHDQ xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm256_unpackhi_epi32 __m256i _mm256_unpackhi_epi32(__m256i __a, __m256i __b)

VPUNPCKHDQ ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_unpackhi_epi32 __m256i _mm256_mask_unpackhi_epi32(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B)

VPUNPCKHDQ ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_unpackhi_epi32 __m256i _mm256_maskz_unpackhi_epi32(__mmask8 __U, __m256i __A, __m256i __B)

VPUNPCKHDQ ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm512_unpackhi_epi32 __m512i _mm512_unpackhi_epi32(__m512i __A, __m512i __B)

VPUNPCKHDQ zmm, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_unpackhi_epi32 __m512i _mm512_mask_unpackhi_epi32(__m512i __W, __mmask16 __U, __m512i __A, __m512i __B)

VPUNPCKHDQ zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_unpackhi_epi32 __m512i _mm512_maskz_unpackhi_epi32(__mmask16 __U, __m512i __A, __m512i __B)

VPUNPCKHDQ zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-502 (PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  9. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.