x86-64.net

Instruction

VPUNPCKHQDQ

Interleaves the high quadwords of each 128-bit lane of two sources.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPUNPCKHQDQ joins the high quadwords of its two sources in each 128-bit lane: the VEX and EVEX form of PUNPCKHQDQ, whose page covers bringing a high half down for a reduction. VPUNPCKLQDQ, its partner, gives what the newer encodings add, three operands, AVX2 for ymm, AVX512F or AVX10.1 for the EVEX forms with masks and a broadcast quadword, and shows the lanes. On Zen 5, vpunpckhqdq ymm0, ymm13, ymm9 gave quadword 1 of each source in the low lane, 786B5E5144372A1Dh and 5C4F4235281B0E01h, and quadword 3 of each in the high one. vpunpckhqdq zmm5{k7}, zmm5, qword bcst [mem] paired each lane’s high quadword of ZMM5 with the broadcast 6227ECB1763B00C5h, writing it into quadwords 1, 5 and 7, which k7 selects, and keeping quadword 3.

In compiled code

In our builds at -O2, the reduction PUNPCKHQDQ’s page shows keeps its shape with VEX: summing the four quadwords of a ymm register with VEXTRACTI128, VPADDQ and _mm_unpackhi_epi64(x, x) gives VPUNPCKHQDQ in GCC 14 and VPSHUFD with EEh in Clang 23, at -march=x86-64-v3 and -v4 alike. GCC’s own reduction of a uint64_t sum loop shifts the high half down with VPSRLDQ instead. Clang also spells _mm256_unpackhi_epi64(a, b) as VUNPCKHPD and (a, a) as VSHUFPS with EEh, where GCC keeps VPUNPCKHQDQ; GCC pairs it with VPUNPCKLQDQ to interleave two int64_t arrays at -v3, and neither compiler unpacks for that at -v4.

Intel’s optimization manual ends its BF16 transposes for AMX with VPUNPCKHQDQ beside VPUNPCKLQDQ on zmm registers, transposing 2x2 blocks of quadwords in every lane at once (Section 20.16, Examples 20-26 to 20-28). AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike one cycle and four per cycle.

Forms

Every encoding of VPUNPCKHQDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPUNPCKHQDQ xmm, xmm, m128 VPUNPCKHQDQ_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG 6D /rAVX
VPUNPCKHQDQ xmm, xmm, xmm VPUNPCKHQDQ_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG 6D /rAVX
VPUNPCKHQDQ ymm, ymm, m256 VPUNPCKHQDQ_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG 6D /rAVX2
VPUNPCKHQDQ ymm, ymm, ymm VPUNPCKHQDQ_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG 6D /rAVX2
VPUNPCKHQDQ zmm {k}{z}, zmm, zmm VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512EVEX.512.66.0F.W1 6D /rAVX10.1 or AVX512F
VPUNPCKHQDQ zmm {k}{z}, zmm, m512/m64bcst VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512EVEX.512.66.0F.W1 6D /rAVX10.1 or AVX512F
VPUNPCKHQDQ xmm {k}{z}, xmm, xmm VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512EVEX.128.66.0F.W1 6D /rAVX10.1 or AVX512F + AVX512VL
VPUNPCKHQDQ xmm {k}{z}, xmm, m128/m64bcst VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512EVEX.128.66.0F.W1 6D /rAVX10.1 or AVX512F + AVX512VL
VPUNPCKHQDQ ymm {k}{z}, ymm, ymm VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512EVEX.256.66.0F.W1 6D /rAVX10.1 or AVX512F + AVX512VL
VPUNPCKHQDQ ymm {k}{z}, ymm, m256/m64bcst VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512EVEX.256.66.0F.W1 6D /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128/m64bcst		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm		ymm, ymm, m256
ymm {k}{z}, ymm, m256/m64bcst		ymm, ymm, ymmzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m64bcst
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p58 / 1p5
Ice Lake7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p151 / 1p58 / 1p5
Alder Lake8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p15
Sapphire Rapids8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p151 / 1p59 / 1p5
Lunar Lake8 / 0.5V2 V31 / 0.5V2 V39 / 0.5V2 V31 / 0.5V2 V3
Piledriver7 / 1.5FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP21 / 1FP1 FP28 / 1FP1 FP2
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the high quadwords of both sources alternate in the result, those of xmm2 in the even places.
VPUNPCKHQDQ: high halves interleavedResult quadwords 1 to 0: b1, a1.01xmm2a11k1a1b1xmm101xmm3or m128b

The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m64bcst, one quadword from memory stands for every element of xmm3.

Result quadwords 1 to 0: b1, a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    j = i - i % 2 + i % 2 // 2 + 1  # in the lane of i
    if k1[i]:                       # 1 without a write mask
        if i % 2 == 0:
            zmm1.q[i] = zmm2.q[j]
        else:
            zmm1.q[i] = src3.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPUNPCKHQDQ xmm, xmm, xmm/m128 VPUNPCKHQDQ ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPUNPCKHQDQ xmm {k}{z}, xmm, xmm/m128/m64bcst VPUNPCKHQDQ ymm {k}{z}, ymm, ymm/m256/m64bcst VPUNPCKHQDQ zmm {k}{z}, zmm, zmm/m512/m64bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m64bcst, ymm/m256/m64bcst, zmm/m512/m64bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPUNPCKHQDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_unpackhi_epi64 __m128i _mm_unpackhi_epi64(__m128i __a, __m128i __b)

VPUNPCKHQDQ xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_unpackhi_epi64 __m128i _mm_mask_unpackhi_epi64(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPUNPCKHQDQ xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_unpackhi_epi64 __m128i _mm_maskz_unpackhi_epi64(__mmask8 __U, __m128i __A, __m128i __B)

VPUNPCKHQDQ xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm256_unpackhi_epi64 __m256i _mm256_unpackhi_epi64(__m256i __a, __m256i __b)

VPUNPCKHQDQ ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_unpackhi_epi64 __m256i _mm256_mask_unpackhi_epi64(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B)

VPUNPCKHQDQ ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_unpackhi_epi64 __m256i _mm256_maskz_unpackhi_epi64(__mmask8 __U, __m256i __A, __m256i __B)

VPUNPCKHQDQ ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm512_unpackhi_epi64 __m512i _mm512_unpackhi_epi64(__m512i __A, __m512i __B)

VPUNPCKHQDQ zmm, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_unpackhi_epi64 __m512i _mm512_mask_unpackhi_epi64(__m512i __W, __mmask8 __U, __m512i __A, __m512i __B)

VPUNPCKHQDQ zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_unpackhi_epi64 __m512i _mm512_maskz_unpackhi_epi64(__mmask8 __U, __m512i __A, __m512i __B)

VPUNPCKHQDQ zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-502 (PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
  9. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.