VPUNPCKHWD

VPUNPCKHWD interleaves the high words of its two sources, a word of the first, a word of the second, and so on: the VEX and EVEX form of PUNPCKHWD, whose page covers the pairings with a zeroed register, with itself and with the high halves of products. VPUNPCKLBW covers what the newer encodings bring; the EVEX forms need AVX512BW (or AVX10.1) and take a write mask per word. Each 128-bit lane takes its own high four words: on Zen 5, vpunpckhwd ymm7, ymm11, ymmword ptr [mem] filled words 8 to 15 of the result from words 12 to 15 of each source, ECDFh from YMM11 and 884Dh from memory first.

Two halves of a doubleword#

Interleaving puts each word of the first source in the low half of a doubleword and the matching word of the second source in the high half. Intel’s optimization manual converts half-precision values to single precision in AVX-128 code that way: it computes the upper and the lower 16 bits of each single in separate registers and joins them with VPUNPCKLWD and VPUNPCKHWD, the conversion that VCVTPH2PS does about 2.5 times as fast (Section 15.14.2, Example 15-33). With zero as the first source, each word lands in the upper half alone, which turns BF16 bits into the single of the same value: _mm256_unpackhi_epi16(_mm256_setzero_si256(), x) stays VPXOR and VPUNPCKHWD in GCC 14 and Clang 23 at -O2, while a loop of (uint32_t)h[i] << 16 compiles to VPMOVZXWD and VPSLLD in both.

In compiled code#

In our builds with -march=x86-64-v3, interleaving two int16_t arrays is VPUNPCKLWD and VPUNPCKHWD of the same two registers in both compilers, followed by two VPERM2I128 in GCC and a VPERM2I128 and a VINSERTI128 in Clang, which put the lanes’ halves in order; with -march=x86-64-v4 both use VPERMT2W instead. AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike one cycle and four per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    j = i - i % 8 + i % 8 // 2 + 4  # in the lane of i
    if k1[i]:                       # 1 without a write mask
        if i % 2 == 0:
            zmm1.w[i] = zmm2.w[j]
        else:
            zmm1.w[i] = src3.w[j]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPUNPCKHWD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSLLQ
• VPSLLW
• VPSRAD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR

All 253 AVX instructions

More AVX2 instructions

• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD

All 686 AVX10.1 instructions