x86-64.net

Instruction

VPUNPCKLBW

Interleaves the low bytes of each 128-bit lane of two sources.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPUNPCKLBW is PUNPCKLBW in VEX and EVEX encodings: it interleaves the low bytes of its two sources, a byte of the first, a byte of the second, and so on. The PUNPCKLBW page covers the interleave and its classic uses, widening against zero and doubling bytes. Above 128 bits, the newer encodings work on each 128-bit lane on its own: every lane interleaves its own low eight bytes. On Zen 5, vpunpcklbw ymm0, ymm13, ymm9 filled bytes 16 to 31 of the result from bytes 16 to 23 of each source, and bytes 8 to 15 of the sources appeared nowhere. A 256-bit result therefore holds source bytes 0 to 7 and 16 to 23, and VPUNPCKHBW the others.

The encodings also bring a separate destination, a memory operand at any address, clearing above the vector width, and, in EVEX, a write mask per byte, which needs AVX512BW (or AVX10.1), not just AVX512F.

In compiled code

The widening for which SSE2 code unpacks against zero has its own instructions since SSE4.1: GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 widen uint8_t to uint16_t with VPMOVZXBW and int8_t with VPMOVSXBW, and emit no unpack at all.

Interleaving two byte arrays is still unpack work, and here the lanes show. For c[2*i] = a[i]; c[2*i+1] = b[i];, both compilers compute VPUNPCKLBW and VPUNPCKHBW of the same two registers, which leaves the four quarters of the output in the wrong order, and repair it with VPERM2I128, GCC twice, Clang once together with VINSERTI128. With -march=x86-64-v4, GCC switches to VPERMT2W and VPSHUFB on zmm registers, while Clang unpacks xmm registers, where lanes do not matter.

AMD’s latency spreadsheet for Zen 5 gives VPUNPCKLBW one cycle, four per cycle at every width, and VPERM2I128, which crosses lanes, 3 cycles and two per cycle. Zen 5’s 10 recorded cases cover every form, merging and zeroing included.

Forms

Every encoding of VPUNPCKLBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPUNPCKLBW xmm, xmm, m128 VPUNPCKLBW_XMMdq_XMMdq_MEMdqVEX.128.66.0F.WIG 60 /rAVX
VPUNPCKLBW xmm, xmm, xmm VPUNPCKLBW_XMMdq_XMMdq_XMMdqVEX.128.66.0F.WIG 60 /rAVX
VPUNPCKLBW ymm, ymm, m256 VPUNPCKLBW_YMMqq_YMMqq_MEMqqVEX.256.66.0F.WIG 60 /rAVX2
VPUNPCKLBW ymm, ymm, ymm VPUNPCKLBW_YMMqq_YMMqq_YMMqqVEX.256.66.0F.WIG 60 /rAVX2
VPUNPCKLBW xmm {k}{z}, xmm, xmm VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512EVEX.128.66.0F.WIG 60 /rAVX10.1 or AVX512BW + AVX512VL
VPUNPCKLBW xmm {k}{z}, xmm, m128 VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512EVEX.128.66.0F.WIG 60 /rAVX10.1 or AVX512BW + AVX512VL
VPUNPCKLBW ymm {k}{z}, ymm, ymm VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512EVEX.256.66.0F.WIG 60 /rAVX10.1 or AVX512BW + AVX512VL
VPUNPCKLBW ymm {k}{z}, ymm, m256 VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512EVEX.256.66.0F.WIG 60 /rAVX10.1 or AVX512BW + AVX512VL
VPUNPCKLBW zmm {k}{z}, zmm, zmm VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512EVEX.512.66.0F.WIG 60 /rAVX10.1 or AVX512BW
VPUNPCKLBW zmm {k}{z}, zmm, m512 VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512EVEX.512.66.0F.WIG 60 /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128no mask		xmm, xmm, xmm
xmm {k}{z}, xmm, xmmno mask
ymm {k}{z}, ymm, ymmno mask		ymm, ymm, m256
ymm {k}{z}, ymm, m256no mask		ymm, ymm, ymmxmm {k}{z}, xmm, xmmwith a mask, zeroing
ymm {k}{z}, ymm, ymmwith a mask, zeroing		xmm {k}{z}, xmm, m128with a mask, zeroingymm {k}{z}, ymm, m256with a mask, zeroingzmm {k}{z}, zmm, zmmno maskzmm {k}{z}, zmm, zmmwith a mask, zeroingzmm {k}{z}, zmm, m512no maskzmm {k}{z}, zmm, m512with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell, Skylake7 / 1p51 / 1p58 / 1p51 / 1p5
Broadwell6 / 1p51 / 1p57 / 1p51 / 1p5
Skylake-SP7 / 1p51 / 1p58 / 1p51 / 1p51 / 1p57 / 1p58 / 1p51 / 1p51 / 1p58 / 1p58 / 1p5
Ice Lake7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p151 / 0.5p157 / 0.5p158 / 0.5p151 / 1p51 / 1p58 / 1p58 / 1p5
Alder Lake8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p15
Sapphire Rapids8 / 0.5p151 / 0.5p159 / 0.5p151 / 0.5p153 / 0.5p1511 / 0.5p1511 / 0.5p151 / 1p53 / 1p59 / 1p511 / 1p5
Lunar Lake8 / 0.5V2 V31 / 0.5V2 V39 / 0.5V2 V31 / 0.5V2 V3
Piledriver7 / 1.5FPU1 FPXBR2 / 1FPU1 FPXBR
Zen8 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 1FPU1 FPU21 / 1FPU1 FPU2
Zen 28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 0.5FPU1 FPU2
Zen 38 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP2
Zen 48 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP21 / 0.5FP1 FP21 / 0.5FP1 FP28 / 0.5FP1 FP28 / 0.5FP1 FP21 / 1FP1 FP21 / 1FP1 FP28 / 1FP1 FP28 / 1FP1 FP2
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Interleave: the low bytes of both sources alternate in the result, those of xmm2 in the even places.
VPUNPCKLBW: low halves interleavedResult bytes 15 to 0: b7, unchanged (bit 14 of k1 is 0), b6, a6, b5, a5, b4, a4, b3, a3, b2, a2, b1, a1, b0, a0.0123456789101112131415xmm2a1111111111111110k1a0a1a2a3a4a5a6b0b1b2b3b4b5b6b7xmm10123456789101112131415xmm3or m128b

The ymm and zmm forms repeat this in each 128-bit lane. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result bytes 15 to 0: b7, unchanged (bit 14 of k1 is 0), b6, a6, b5, a5, b4, a4, b3, a3, b2, a2, b1, a1, b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    j = i - i % 16 + i % 16 // 2  # in the lane of i
    if k1[i]:                     # 1 without a write mask
        if i % 2 == 0:
            zmm1.b[i] = zmm2.b[j]
        else:
            zmm1.b[i] = src3.b[j]
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPUNPCKLBW xmm, xmm, xmm/m128 VPUNPCKLBW ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPUNPCKLBW xmm {k}{z}, xmm, xmm/m128 VPUNPCKLBW ymm {k}{z}, ymm, ymm/m256 VPUNPCKLBW zmm {k}{z}, zmm, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPUNPCKLBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_unpacklo_epi8 __m128i _mm_unpacklo_epi8(__m128i __a, __m128i __b)

VPUNPCKLBW xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_unpacklo_epi8 __m128i _mm_mask_unpacklo_epi8(__m128i __W, __mmask16 __U, __m128i __A, __m128i __B)

VPUNPCKLBW xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_unpacklo_epi8 __m128i _mm_maskz_unpacklo_epi8(__mmask16 __U, __m128i __A, __m128i __B)

VPUNPCKLBW xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_unpacklo_epi8 __m256i _mm256_unpacklo_epi8(__m256i __a, __m256i __b)

VPUNPCKLBW ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_unpacklo_epi8 __m256i _mm256_mask_unpacklo_epi8(__m256i __W, __mmask32 __U, __m256i __A, __m256i __B)

VPUNPCKLBW ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_unpacklo_epi8 __m256i _mm256_maskz_unpacklo_epi8(__mmask32 __U, __m256i __A, __m256i __B)

VPUNPCKLBW ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_unpacklo_epi8 __m512i _mm512_unpacklo_epi8(__m512i __A, __m512i __B)

VPUNPCKLBW zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_unpacklo_epi8 __m512i _mm512_mask_unpacklo_epi8(__m512i __W, __mmask64 __U, __m512i __A, __m512i __B)

VPUNPCKLBW zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_unpacklo_epi8 __m512i _mm512_maskz_unpacklo_epi8(__mmask64 __U, __m512i __A, __m512i __B)

VPUNPCKLBW zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-512 (PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.