VPUNPCKLWD

VPUNPCKLWD is the VEX and EVEX form of PUNPCKLWD: it interleaves the low words of its two sources, a word of the first, a word of the second, and so on. VPUNPCKLBW covers what the newer encodings bring and how they work on each 128-bit lane; the EVEX forms need AVX512BW (or AVX10.1) and take a write mask per word. On Zen 5, vpunpcklwd ymm12, ymm6, ymmword ptr [mem] filled words 8 to 15 of the result from words 8 to 11 of each source, B075h, 26EBh, 9C61h and 12D7h from memory among them, and memory words 4 to 7 appeared nowhere.

Two halves of a product#

A 16-bit multiply has a 32-bit result, which SSE2 computes in halves: VPMULLW gives the low words and VPMULHW, or VPMULHUW for unsigned numbers, the high ones. In our builds at -O2 with -march=x86-64-v3, GCC 14 compiles c[i] = a[i] * b[i] from int16_t or uint16_t factors into 32-bit results that way, joins the halves with VPUNPCKLWD and VPUNPCKHWD, which work within lanes, so that the first holds products 0 to 3 and 8 to 11, and restores the order with two VPERM2I128. With -march=x86-64-v4 it widens the factors instead and multiplies doublewords, and Clang 23 widens at both levels, as VPMOVZXWD’s page describes.

Transposing#

Intel’s optimization manual transposes 8x8 matrices of 16-bit elements with AVX2 by loading rows into both lanes with VINSERTI128, interleaving words with VPUNPCKLWD and VPUNPCKHWD, then doublewords, and fixing the order with VPERMQ; its AVX-512 version needs two VPERMI2W per matrix and is reported 2.7 times as fast (Section 17.8.1, Example 17-17).

AMD’s latency spreadsheet for Zen 5 gives VPUNPCKLWD one cycle and four per cycle at every width. Zen 5’s 10 recorded cases cover every form, merging and zeroing included.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    j = i - i % 8 + i % 8 // 2  # in the lane of i
    if k1[i]:                   # 1 without a write mask
        if i % 2 == 0:
            zmm1.w[i] = zmm2.w[j]
        else:
            zmm1.w[i] = src3.w[j]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPUNPCKLWD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS

All 253 AVX instructions

More AVX2 instructions

• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPXOR

All 138 AVX2 instructions

More AVX10.1 instructions

• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH

All 686 AVX10.1 instructions