VPXOR

VPXOR computes the bitwise exclusive OR of two 128- or 256-bit values into a third register. It is the VEX form of PXOR, with a separate destination, a memory operand at any address and, for the 128-bit form, the bits from 128 up cleared. Like every bitwise operation it does not care about element boundaries, so one instruction serves bytes, words, doublewords and quadwords alike. AVX-512 has no EVEX VPXOR: VPXORD and VPXORQ are the same operation, differing only in the element size of the write mask.

Zeroing#

vpxor xmm0, xmm0, xmm0 is the usual way to clear a vector register. The result does not depend on the old value, which processors recognize (see the page’s lines from the optimization guide), and the VEX encoding clears the whole register: on Zen 5, vpxor xmm4, xmm4, xmm4 left all 512 bits of ZMM4 zero. GCC 14 at -O2 uses it for _mm256_setzero_si256 and even for the 512-bit _mm512_setzero_si512, since the short xmm form clears a zmm register too, and for the accumulators of vectorized sums. Clang 23 zeroes the accumulators the same way but uses VXORPS for the two intrinsics.

Comparing and inverting#

Both compilers use VPXOR for memcmp(p, q, 32) == 0 with -march=x86-64-v3: a load, VPXOR with the other block as its memory operand, then VPTEST of the result with itself and SETE. For a[i] = b[i] ^ c[i] over unsigned arrays, GCC 14 emits VPXOR and Clang 23 VXORPS, the same bits by another encoding. AVX2 has no NOT: GCC and Clang invert a vector by XOR with all ones made by VPCMPEQD of a register with itself; with -march=x86-64-v4 both use VPTERNLOGQ instead, and GCC switches the XOR of the loop to VPXORD on zmm registers.

AMD’s latency spreadsheet for Zen 5 gives VPXOR one cycle and four per cycle on any of the four vector pipes. Zen 5’s 4 recorded cases cover the register and memory forms at both widths.

In the optimization guide

What the optimization guide says about VPXOR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Zeroing and dependency-breaking idioms: The vector registers have idioms of their own: pxor, xorps, xorpd, pandn, andnps, the integer subtractions psub and the comparisons pcmpgt of a register with itself, with their VEX and EVEX forms, which Intel counts for 512-bit registers only unmasked. sources differ

Zen 3

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole XMM and YMM registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value; sbb eax, eax depends only on the carry flag, and pcmpeqd xmm0, xmm0 sets all ones without waiting. sources differ

Zen 4

• Integer execution: Register-to-register moves of general registers of 32 and 64 bits, xchg of them and moves of whole vector registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value; sbb eax, eax depends only on the carry flag. sources differ

Zen 5

• Integer execution: Register-to-register moves of 32-bit and 64-bit general registers and of whole vector registers take no execution cycle, nor do the zeroing idioms such as xor eax, eax and vpxor, which also break the dependency on the old value.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    ymm1.q[i] = ymm2.q[i] ^ src3.q[i]
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPXOR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSRLDQ
• VPSRLQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD

All 253 AVX instructions

More AVX2 instructions

• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD
• VPSHUFHW
• VPSHUFLW
• VPSIGNB
• VPSIGND
• VPSIGNW
• VPSLLD
• VPSLLDQ
• VPSLLQ
• VPSLLVD
• VPSLLVQ
• VPSLLW
• VPSRAD
• VPSRAVD
• VPSRAW
• VPSRLD
• VPSRLDQ
• VPSRLQ
• VPSRLVD
• VPSRLVQ
• VPSRLW
• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD

All 138 AVX2 instructions