x86-64.net

Instruction

VPXORD

Computes the bitwise XOR of two vectors, masked at doubleword granularity.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPXORD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPXORD zmm {k}{z}, zmm, zmm VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512EVEX.512.66.0F.W0 EF /rAVX10.1 or AVX512F
VPXORD zmm {k}{z}, zmm, m512/m32bcst VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512EVEX.512.66.0F.W0 EF /rAVX10.1 or AVX512F
VPXORD xmm {k}{z}, xmm, xmm VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512EVEX.128.66.0F.W0 EF /rAVX10.1 or AVX512F + AVX512VL
VPXORD xmm {k}{z}, xmm, m128/m32bcst VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512EVEX.128.66.0F.W0 EF /rAVX10.1 or AVX512F + AVX512VL
VPXORD ymm {k}{z}, ymm, ymm VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512EVEX.256.66.0F.W0 EF /rAVX10.1 or AVX512F + AVX512VL
VPXORD ymm {k}{z}, ymm, m256/m32bcst VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512EVEX.256.66.0F.W0 EF /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPXORD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mask_xor_epi32 __m128i _mm_mask_xor_epi32(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B)

VPXORD xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_mask_xor_ps __m128 _mm_mask_xor_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)

VPXORD xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512dq

_mm_maskz_xor_epi32 __m128i _mm_maskz_xor_epi32(__mmask8 __U, __m128i __A, __m128i __B)

VPXORD xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_xor_ps __m128 _mm_maskz_xor_ps(__mmask8 __U, __m128 __A, __m128 __B)

VPXORD xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512dq

_mm256_mask_xor_epi32 __m256i _mm256_mask_xor_epi32(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B)

VPXORD ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_mask_xor_ps __m256 _mm256_mask_xor_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B)

VPXORD ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512dq

_mm256_maskz_xor_epi32 __m256i _mm256_maskz_xor_epi32(__mmask8 __U, __m256i __A, __m256i __B)

VPXORD ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_xor_ps __m256 _mm256_maskz_xor_ps(__mmask8 __U, __m256 __A, __m256 __B)

VPXORD ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512dq

_mm512_xor_epi32 __m512i _mm512_xor_epi32(__m512i __a, __m512i __b)

VPXORD zmm, zmm, zmm EVEX.512 -mavx512fClang emits the equivalent VPXORQ

_mm512_xor_ps __m512 _mm512_xor_ps(__m512 __A, __m512 __B)

VPXORD zmm, zmm, zmm EVEX.512 -mavx512dq

_mm512_mask_xor_epi32 __m512i _mm512_mask_xor_epi32(__m512i __src, __mmask16 __k, __m512i __a, __m512i __b)

VPXORD zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_xor_ps __m512 _mm512_mask_xor_ps(__m512 __W, __mmask16 __U, __m512 __A, __m512 __B)

VPXORD zmm {k}, zmm, zmm EVEX.512 -mavx512dq

_mm512_maskz_xor_epi32 __m512i _mm512_maskz_xor_epi32(__mmask16 __k, __m512i __a, __m512i __b)

VPXORD zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_xor_ps __m512 _mm512_maskz_xor_ps(__mmask16 __U, __m512 __A, __m512 __B)

VPXORD zmm {k}{z}, zmm, zmm EVEX.512 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.