VPXORD

VPXORD is the EVEX form of VPXOR: the bitwise exclusive OR of two 128-, 256- or 512-bit values, with a write mask that selects doublewords and a memory operand that may be one doubleword repeated to every element. VPXORQ is the same with quadwords; unmasked, the two give the same bits. VPANDD shows what the EVEX forms add and how GCC 14 and Clang 23 choose among the names.

Zeroing#

XOR of a register with itself gives zero, and the VPXOR page describes that idiom. EVEX matters for it in two ways:

• Registers 16 to 31 have no VEX encoding. When every lower register is in use, GCC 14 at -O2 zeroes ZMM16 with vpxord xmm16, xmm16, xmm16 under -march=x86-64-v4, and both compilers with vpxord zmm16, zmm16, zmm16 under -mavx512f, which lacks the AVX512VL needed for the shorter forms.
• A mask makes the old value matter again. On Zen 5, vpxord zmm5{k6}, zmm5, zmm5 with 43A4h in the low 16 bits of K6 cleared doublewords 2, 5, 7, 8, 9 and 14 and kept the other ten.

Intel’s optimization manual breaks a false dependency with an unmasked vpxord zmm3, zmm3, zmm3, which it calls a zero idiom (Section 2.4.1.2, Example 2-5), though its list of 512-bit zero idioms names VPXOR (Section 3.5.1.7). AMD’s Zen 5 guide likewise lists VPXOR with zmm operands among the zeroing idioms that take no cycle (Section 2.9.2); VPXOR has no 512-bit encoding, so both lists can only mean the EVEX forms.

In compiled code#

With -march=x86-64-v4, GCC uses VPXORD for a[i] = b[i] ^ c[i] over int arrays and in the last steps of a vectorized XOR of 32-bit values, where it folds the halves of a zmm register with VEXTRACTI32X8 and VEXTRACTI32X4, each followed by VPXORD. For a test of two vectors for equality it emits VPXORD and a VPTESTMQ of the result.

AMD’s Zen 5 latency spreadsheet gives the EVEX row of VPXORD one cycle and four per cycle on any of the four vector pipes. Zen 5’s 6 recorded cases cover the register and memory forms, broadcast included, at all three widths.

In the optimization guide

What the optimization guide says about VPXORD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Zeroing and dependency-breaking idioms: The vector registers have idioms of their own: pxor, xorps, xorpd, pandn, andnps, the integer subtractions psub and the comparisons pcmpgt of a register with itself, with their VEX and EVEX forms, which Intel counts for 512-bit registers only unmasked. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = zmm2.d[i] ^ src3.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPXORD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSUBUSW
• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS

All 686 AVX10.1 instructions