VPXORQ

VPXORQ is VPXORD with quadwords: the bitwise exclusive OR of two 128-, 256- or 512-bit values, with a write mask that selects quadwords and a memory operand that may be one quadword repeated to every element ({1to8} at 512 bits). The VPXORD page covers zeroing with EVEX, and VPANDD how the compilers choose between the D and Q names; unmasked, the two give the same bits.

Inverting and flipping signs#

XOR with all ones inverts, and the broadcast makes all ones a single quadword in memory. On Zen 5, vpxorq zmm1{k2}, zmm2, qword bcst [mem] with all ones in memory and C9h in the low byte of K2 inverted quadwords 0, 3, 6 and 7 of ZMM2 into ZMM1 and kept the other four of ZMM1: a NOT of the selected elements. For a plain ~q[i] loop GCC 14 uses VPTERNLOGQ instead, while Clang 23 with -mavx512f builds all ones in a register and XORs with VPXORQ.

Without AVX512DQ there is no EVEX VXORPD, so with -mavx512f both compilers negate an array of doubles with VPXORQ against a broadcast sign bit; with -march=x86-64-v4 GCC uses VXORPD and Clang VXORPS. Clang also turns a 16-bit constant repeated across a vector into one quadword: with -mavx512f it compiles _mm512_xor_si512(x, _mm512_set1_epi16(0x7fff)) to VPXORQ with a {1to8} operand, where GCC broadcasts a doubleword into a register.

Folding an XOR reduction#

GCC 14 at -O2 with -march=x86-64-v4 ends a vectorized XOR of 64-bit values, a checksum for example, by halving the zmm register twice with VEXTRACTI64X4 and VEXTRACTI64X2, each followed by VPXORQ, then a VPSRLDQ by 8 bytes and a last VPXORQ. With -mavx512f alone, which lacks AVX512VL and AVX512DQ, it continues after the VEXTRACTI64X4 with VEX VPXOR and VEXTRACTI128.

AMD’s Zen 5 latency spreadsheet gives the EVEX row of VPXORQ one cycle and four per cycle on any of the four vector pipes. Zen 5’s 6 recorded cases cover the register and memory forms, broadcast included, at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = zmm2.q[i] ^ src3.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPXORQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPSUBW
• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD

All 686 AVX10.1 instructions