VRANGEPD

VRANGEPD is VRANGEPS for doubles: for each pair it picks the smaller or the larger value, by value or by magnitude, as immediate bits 1:0 say, then sets the sign as bits 3:2 say, from the first source, from the chosen value, cleared or set. That page gives the useful immediates and the rules for zeros and NaNs. It came with AVX512DQ, together with the scalar VRANGESD. The SDM’s example for it is vrangepd zmm_dst, zmm_src, zmm_1023, 02h, which limits each double to the range -1023 to 1023 in one instruction: the smaller magnitude, with the sign of the input.

Recorded on Zen 5#

• The clamp. With immediate 02h, 3.0 against a bound of -4.0 gave 3.0 and -3.0 against 4.0 gave -3.0; -2.0 against 2.0 gave -2.0 and 2.0 against -2.0 gave 2.0, since of x and -x the smaller magnitude is -x and the sign then comes from the first source.
• The sign set. Immediate 0Ch, the minimum with the sign set, gave -1.0 for 1.0 paired with itself.
• Signaling NaNs. 1.0 against the broadcast signaling NaN 7FF0000000012345h gave the NaN quieted, 7FF8000000012345h, and set IE. The immediate was 1Ah, with bit 4 set, a bit the SDM says must be zero; Zen 5 did not fault.
• DAZ. With DAZ set and immediate 02h, the largest denormal against 2^-1022 gave +0, and under immediate 06h the denormal 8008000000000000h against 1.0 gave -0, without DE.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 emit VRANGEPD only for the intrinsics, such as _mm512_range_pd(a, b, 2). A loop of fmax becomes VMAXPD with a NaN fix-up in Clang, and a pick by magnitude with copysign becomes compares, VPTERNLOGQ and VBLENDMPD in GCC.

AMD’s Zen 5 latency spreadsheet gives every width one macro-op on pipe FP2 or FP3 and 2 cycles, two per cycle, as for VRANGEPS.

In the optimization guide

What the optimization guide says about VRANGEPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm2.f64[i]
        b = src3.f64[i]
        zmm1.f64[i] = frange(a, b, imm8)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# imm8[1:0]: min, max, min |x|, max |x|; [3:2]: sign of a, of the result, 0, 1
# m64bcst: src3.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRANGEPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPTERNLOGD
• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH

All 686 AVX10.1 instructions