VRANGEPS

VRANGEPS picks, for each pair of singles, the smaller or the larger, by value or by magnitude, and then sets the sign of the result. Bits 1:0 of the immediate choose the comparison: minimum, maximum, minimum of the absolute values or maximum of the absolute values. Bits 3:2 choose the sign: that of the first source (00), that of the chosen value (01), cleared (10) or set (11). It came with AVX512DQ, together with VRANGEPD and the scalar VRANGESS and VRANGESD; AVX10.2’s VMINMAXPS uses the same sign field.

Useful immediates#

The trap is that 00h and 01h are not plain minimum and maximum: they keep the sign of the first source. In a case recorded on Zen 5, immediate 01h on -2 and 1 gave -1: the maximum, 1, with the sign of -2. With 02h and a bound in b, a is limited to a symmetric range in one instruction.

Zeros and NaNs#

Unlike MINPS and MAXPS, which return their second source for a NaN or two zeros, VRANGEPS treats both orders alike. -0 counts as less than +0, whichever operand holds it; and for the magnitude comparisons, of x and -x the minimum is -x and the maximum x. A quiet NaN loses to a number, as in IEEE 754-2008’s minNum; a signaling NaN is returned quieted and sets the invalid flag, and then the sign field is ignored. Zen 5 turned 7F812345h against 1.0 into 7FC12345h and set IE, and 7FC12345h against 1.0 into 1.0. A denormal input sets DE, or counts as a zero under DAZ; {sae} suppresses the flags.

In compiled code#

GCC 14 and Clang 23 emit VRANGEPS only for the intrinsics, such as _mm512_range_ps(a, b, imm), with AVX512DQ enabled (x86-64-v4 has it). Loops of fmaxf, of a clamp with copysignf or of a pick by magnitude become compares, blends and VPTERNLOGD instead.

Intel’s optimization manual counts VRANGE among the instructions that wait for the old value of their destination on Golden Cove, and recommends zeroing that register first (Section 2.4.1.2). AMD’s Zen 5 guide lists VRANGEPS as one macro-op with a latency of 2 cycles, the same as VMAXPS.

In the optimization guide

What the optimization guide says about VRANGEPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm2.f32[i]
        b = src3.f32[i]
        zmm1.f32[i] = frange(a, b, imm8)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# imm8[1:0]: min, max, min |x|, max |x|; [3:2]: sign of a, of the result, 0, 1
# m32bcst: src3.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRANGEPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPTERNLOGQ
• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS

All 686 AVX10.1 instructions