x86-64.net

Instruction

VRANGEPS

Computes the minimum, maximum, or value of smaller or larger magnitude of packed singles, as an immediate selects along with the sign of the result.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VRANGEPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VRANGEPS xmm {k}{z}, xmm, xmm, imm8 VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512EVEX.128.66.0F3A.W0 50 /r ibAVX10.1 or AVX512DQ + AVX512VL
VRANGEPS xmm {k}{z}, xmm, m128/m32bcst, imm8 VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512EVEX.128.66.0F3A.W0 50 /r ibAVX10.1 or AVX512DQ + AVX512VL
VRANGEPS ymm {k}{z}, ymm, ymm, imm8 VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512EVEX.256.66.0F3A.W0 50 /r ibAVX10.1 or AVX512DQ + AVX512VL
VRANGEPS ymm {k}{z}, ymm, m256/m32bcst, imm8 VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512EVEX.256.66.0F3A.W0 50 /r ibAVX10.1 or AVX512DQ + AVX512VL
VRANGEPS zmm {k}{z}, zmm, zmm, imm8, {sae} VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512EVEX.512.66.0F3A.W0 50 /r ibAVX10.1 or AVX512DQ
VRANGEPS zmm {k}{z}, zmm, m512/m32bcst, imm8 VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512EVEX.512.66.0F3A.W0 50 /r ibAVX10.1 or AVX512DQ

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRANGEPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_range_ps __m128 _mm_range_ps(__m128 A, __m128 B, const int C)

VRANGEPS xmm, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512dq

_mm_mask_range_ps __m128 _mm_mask_range_ps(__m128 W, __mmask8 U, __m128 A, __m128 B, const int C)

VRANGEPS xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512dq

_mm_maskz_range_ps __m128 _mm_maskz_range_ps(__mmask8 U, __m128 A, __m128 B, const int C)

VRANGEPS xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx512vl -mavx512dq

_mm256_range_ps __m256 _mm256_range_ps(__m256 A, __m256 B, const int C)

VRANGEPS ymm, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512dq

_mm256_mask_range_ps __m256 _mm256_mask_range_ps(__m256 W, __mmask8 U, __m256 A, __m256 B, const int C)

VRANGEPS ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512dq

_mm256_maskz_range_ps __m256 _mm256_maskz_range_ps(__mmask8 U, __m256 A, __m256 B, const int C)

VRANGEPS ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx512vl -mavx512dq

_mm512_range_ps __m512 _mm512_range_ps(__m512 A, __m512 B, const int C)

VRANGEPS zmm, zmm, zmm, imm8 EVEX.512 -mavx512dq

_mm512_range_round_ps __m512 _mm512_range_round_ps(__m512 A, __m512 B, const int C, const int R)

VRANGEPS zmm, zmm, zmm, imm8, {sae} EVEX.512 -mavx512dq

_mm512_mask_range_ps __m512 _mm512_mask_range_ps(__m512 W, __mmask16 U, __m512 A, __m512 B, const int C)

VRANGEPS zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx512dq

_mm512_mask_range_round_ps __m512 _mm512_mask_range_round_ps(__m512 W, __mmask16 U, __m512 A, __m512 B, const int C, const int R)

VRANGEPS zmm {k}, zmm, zmm, imm8, {sae} EVEX.512 -mavx512dq

_mm512_maskz_range_ps __m512 _mm512_maskz_range_ps(__mmask16 U, __m512 A, __m512 B, const int C)

VRANGEPS zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx512dq

_mm512_maskz_range_round_ps __m512 _mm512_maskz_range_round_ps(__mmask16 U, __m512 A, __m512 B, const int C, const int R)

VRANGEPS zmm {k}{z}, zmm, zmm, imm8, {sae} EVEX.512 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512DQ_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512DQ_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512DQ_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.