VRANGESD

VRANGESD does what VRANGEPD does to the low double only: of the low doubles of its two sources it picks the smaller or the larger, by value or by magnitude, as immediate bits 1:0 say, and sets the sign as bits 3:2 say. VRANGEPS gives the useful immediates and the rules for zeros and NaNs. The upper double of the result comes from the first source, as in the other EVEX scalar instructions, and a write mask decides only the low one. The second source is an XMM register or 8 bytes of memory, and the register form takes {sae}. It came with AVX512DQ; VRANGESS is the single-precision form.

Recorded on Zen 5#

• Magnitudes. With immediate 03h, the larger magnitude with the sign of the first source, 2.0 against -2.0 from memory gave 2.0, under zeroing masking with bit 0 of K5 set.
• The upper double. In vrangesd xmm17{k3}, xmm30, xmm2, {sae}, 0x6, 1.0 against 1.0 gave 1.0, and the upper double, -1.0, came from XMM30; MXCSR stayed unchanged.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 emit VRANGESD only for the intrinsics: _mm_range_sd(x, y, 2) is vrangesd xmm0, xmm0, xmm1, 2. fmin(fabs(x), fabs(y)) becomes VMINSD on the absolute values in Clang, followed by a compare for NaNs, and a call to fmin in GCC.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP2 or FP3 and 2 cycles, two per cycle, as for VRANGEPD.

In the optimization guide

What the optimization guide says about VRANGESD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f64[0]
    b = src3.f64[0]
    xmm1.f64[0] = frange(a, b, imm8)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# imm8[1:0]: min, max, min |x|, max |x|; [3:2]: sign of a, of the result, 0, 1
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRANGESD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPTESTMB
• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD

All 686 AVX10.1 instructions