Instruction
VRANGESS
Computes the minimum, maximum, or smaller or larger magnitude of the low singles, as an immediate selects; the rest come from the first source.
- Extensions
- Forms
- 2 (2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VRANGESS xmm {k}{z}, xmm, xmm, imm8, {sae}
VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | EVEX.LIG.66.0F3A.W0 51 /r ib | AVX10.1 or AVX512DQ |
VRANGESS xmm {k}{z}, xmm, m32, imm8
VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | EVEX.LIG.66.0F3A.W0 51 /r ib | AVX10.1 or AVX512DQ |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VRANGESS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_range_round_ss
__m128 _mm_range_round_ss(__m128 A, __m128 B, const int C, const int R) |
|
_mm_range_ss
__m128 _mm_range_ss(__m128 A, __m128 B, const int C) |
|
_mm_mask_range_round_ss
__m128 _mm_mask_range_round_ss(__m128 W, __mmask8 U, __m128 A, __m128 B, const int C, const int R) |
|
_mm_mask_range_ss
__m128 _mm_mask_range_ss(__m128 W, __mmask8 U, __m128 A, __m128 B, const int C) |
|
_mm_maskz_range_round_ss
__m128 _mm_maskz_range_round_ss(__mmask8 U, __m128 A, __m128 B, const int C, const int R) |
|
_mm_maskz_range_ss
__m128 _mm_maskz_range_ss(__mmask8 U, __m128 A, __m128 B, const int C) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512DQ_SCALAR | AVX10.1 or AVX512DQ | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VPTESTMD
- VPTESTMQ
- VPTESTMW
- VPTESTNMB
- VPTESTNMD
- VPTESTNMQ
- VPTESTNMW
- VPUNPCKHBW
- VPUNPCKHDQ
- VPUNPCKHQDQ
- VPUNPCKHWD
- VPUNPCKLBW
- VPUNPCKLDQ
- VPUNPCKLQDQ
- VPUNPCKLWD
- VPXORD
- VPXORQ
- VRANGEPD
- VRANGEPS
- VRANGESD
- VRCP14PD
- VRCP14PS
- VRCP14SD
- VRCP14SS
- VRCPPH
- VRCPSH
- VREDUCEPD
- VREDUCEPH
- VREDUCEPS
- VREDUCESD
- VREDUCESH
- VREDUCESS
- VRNDSCALEPD
- VRNDSCALEPH
- VRNDSCALEPS
- VRNDSCALESD
- VRNDSCALESH
- VRNDSCALESS
- VRSQRT14PD
- VRSQRT14PS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.