VRANGESS

VRANGESS does what VRANGEPS does to the low single only: it picks the smaller or the larger of the two low singles, by value or by magnitude, as immediate bits 1:0 say, and sets the sign as bits 3:2 say; that page gives the useful immediates and the rules for zeros and NaNs. Bits 127:32 of the result come from the first source, and a write mask decides only the low single, so zeroing masking clears it alone. The second source is an XMM register or 4 bytes of memory, and the register form takes {sae}. It came with AVX512DQ, together with the double form VRANGESD.

Recorded on Zen 5#

• The sign cleared. vrangess xmm24{k4}, xmm3, xmm3, {sae}, 0x1a gave 1.0 for -1.0 paired with itself: the smaller magnitude, sign cleared. Bit 4 of the immediate, which the SDM says must be zero, changed nothing.
• Zeroing. In vrangess xmm17{k6}{z}, xmm30, dword ptr [...], 0x8 bit 0 of K6 was clear: the low single became 0, and 0.5, a quiet NaN and 1.0 above it came from XMM30 unchanged.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 emit VRANGESS only for the intrinsics: _mm_range_ss(x, y, 2) is vrangess xmm0, xmm0, xmm1, 2.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP2 or FP3 and 2 cycles, two per cycle, the figures of every VRANGE row.

In the optimization guide

What the optimization guide says about VRANGESS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: VPERMD, VPERMQ, VPERMPS, VPERMPD, VPMULLQ, vrange, vgetmant and the half-precision complex multiplications wait for the old value of their destination, which they then overwrite.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f32[0]
    b = src3.f32[0]
    xmm1.f32[0] = frange(a, b, imm8)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {sae}: no exception flags
# imm8[1:0]: min, max, min |x|, max |x|; [3:2]: sign of a, of the result, 0, 1
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRANGESS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPTESTMD
• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS

All 686 AVX10.1 instructions