VRCP14PD

VRCP14PD estimates 1/x for each double, with a relative error of at most 2^-14. It is the double form of VRCP14PS, whose page explains that only the bound is architectural and how a Newton-Raphson step refines an estimate. Before AVX-512 there was no reciprocal estimate for doubles at all: RCPPS and VRCPPS work on singles only. The worst of the 19 results recorded on Zen 5 for this page is 0.5 times 2^-14.

Special inputs on Zen 5#

• Zeros, infinities and NaNs. +0 and -0 gave infinities of their sign, infinities gave zeros of theirs, and the signaling NaN 7FF0000000012345h came back quiet as 7FF8000000012345h, with MXCSR unchanged.
• Exact cases. Powers of two came back exact, 0.5 as 2.0 and 2^-1022 as 2^1022.
• The ends of the range. Without FTZ, the largest double gave 0004000000000000h, the denormal 2^-1024, with no flag set although MXCSR 0 unmasked every exception. Without DAZ, a denormal input is a number: the smallest gave +infinity and 0004000000000001h gave 7FEFFFC000000000h, near the largest double. Under DAZ every denormal gave an infinity, and under FTZ the reciprocal of 2^1023 gave 0.

Division#

Intel’s optimization manual counts the cost of a quotient by accuracy (Table 17-12): VRCP14PD and a multiplication give 14 bits, one Newton-Raphson iteration 26 and two of them 52, while all 53 take VDIVPD. Its Section 17.15.1 notes that the legacy estimates would need three iterations for doubles, and suggests a rounded VRCP14PD in place of a reciprocal table in the argument reduction of log or cbrt.

Unlike singles, doubles get no estimate from the compilers: GCC 14 and Clang 23 at -O2 with -ffast-math, for -march=x86-64-v4 or -march=znver5, compile both a[i] / b[i] and 1.0 / b[i] over double arrays to VDIVPD. VRCP14PD comes from _mm512_rcp14_pd and its 128- and 256-bit kin.

AMD’s Zen 5 latency spreadsheet gives VRCP14PD 5 cycles and two per cycle on pipes FP1 and FP2, as VRCP14PS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.f64[i] = rcp14(src2.f64[i])
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# rcp14: 1/a within 2^-14; Zen 5's 19
# recorded results: 0.5000 * 2^-14 at most
# denormals and tiny results by MXCSR.DAZ and FTZ; no flags
# m64bcst: src2.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRCP14PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPTESTMQ
• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD

All 686 AVX10.1 instructions