VRCP14PS

VRCP14PS estimates 1/x for each single, with a relative error of at most 2^-14. Only that bound is architectural: the bits of an estimate belong to the processor, so the same input may give different results on Intel and AMD cores. The worst of the 59 results recorded on Zen 5 for this page is 0.8911 times 2^-14. Exact powers of two come back exact; Zen 5 turned 2.0 into 0.5 and 0.5 into 2.0.

It is AVX-512’s successor to RCPPS and VRCPPS, whose bound is 1.5 times 2^-12, about six times looser, and which have no zmm form, no masking and no double version; VRCP14PD is the double one.

Special inputs and flags#

A zero gives an infinity of its sign, an infinity a zero of its sign, and a NaN comes back quiet. The instruction sets no MXCSR flag at all, not even for an SNaN: Zen 5 quieted 7F812345h to 7FC12345h and left MXCSR as it was. Denormals follow DAZ and FTZ: under DAZ a denormal input counts as a zero, and the inputs above 2^126 have reciprocals below the normal range, which Zen 5 returned as denormals (the largest single gave 00200000h) and, under FTZ, as zeros.

Division and Newton-Raphson#

One Newton-Raphson step, r’ = r(2 - xr), roughly doubles the correct bits, so VRCP14PS plus one step comes close to single precision. Intel’s optimization manual recommends that sequence where throughput matters more than full precision, and notes that doubles need two steps from VRCP14PD instead of three from older estimates (Sections 17.15.1 and 17.25).

Compilers do this for division under -ffast-math. For a loop of a[i] / b[i] with -march=x86-64-v4, GCC 14 at -O2 emits VRCP14PS on zmm registers, one Newton step and a multiplication by a[i]; Clang 23 does the same with -march=znver5, the step done with VFNMADD213PS, but with -march=x86-64-v4 it uses VRCPPS on ymm registers. Since the step starts from the processor’s estimate, such a quotient can differ in its last bit between processors, where VDIVPS always gives the correctly rounded result.

AMD’s Zen 5 guide lists VRCP14PS as one macro-op with a latency of 5 cycles, against 4 for VRCPPS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.f32[i] = rcp14(src2.f32[i])
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# rcp14: 1/a within 2^-14; Zen 5's 59
# recorded results: 0.8911 * 2^-14 at most
# denormals and tiny results by MXCSR.DAZ and FTZ; no flags
# m32bcst: src2.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRCP14PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPTESTMW
• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS

All 686 AVX10.1 instructions