VRCP14SD

VRCP14SD estimates 1/x for the low double of its second source, within a relative error of 2^-14, and copies bits 127:64 from the first source. It is the scalar form of VRCP14PD, whose page gives the special inputs, and VRCP14PS explains that only the bound is architectural. The EVEX encoding adds a write mask on the one element and xmm16 to xmm31, and clears the register from bit 128 up. No MXCSR flag is ever set, and DAZ and FTZ apply. VRCP14SS is the single-precision form; before AVX-512 there was no scalar reciprocal estimate for doubles, only VRCPSS for singles.

Recorded on Zen 5#

• A denormal is a number. Without DAZ, 0007C667FFF95720h gave 7FE076C000000000h, 0.89 times 2^-14 above the true value, with 14 significand bits and 38 zero bits after them. The smallest denormal gave +infinity, and no flag was set.
• DAZ and FTZ. Under DAZ the largest denormal counted as zero and gave +infinity; under FTZ, 2^1023 gave 0, since 2^-1023 is a denormal.
• An SNaN. With every exception unmasked, the signaling NaN 7FF0000000012345h came back quiet as 7FF8000000012345h, without a fault.
• Masked off. With bit 0 of K5 clear, the merge kept the low double of the destination and still took bits 127:64 from the first source.

In compiled code#

At -O2 with -march=x86-64-v4, even with -ffast-math and -mrecip, GCC 14 and Clang 23 compile 1.0 / x on a double to VDIVSD. VRCP14SD comes from _mm_rcp14_sd(a, b), which both compile to one VRCP14SD with a as the first source, and from its masked forms.

AMD’s Zen 5 latency spreadsheet gives one macro-op and 5 cycles, two per cycle on pipes FP1 and FP2, as for VRCP14PD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f64[0] = rcp14(src3.f64[0])
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# rcp14: 1/a within 2^-14; Zen 5's 2
# recorded results: 0.8921 * 2^-14 at most
# denormals and tiny results by MXCSR.DAZ and FTZ; no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRCP14SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPTESTNMB
• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH

All 686 AVX10.1 instructions