VRCP14SS

VRCP14SS estimates 1/x for the low single of its second source, within a relative error of 2^-14, and copies bits 127:32 from the first source. It is the scalar form of VRCP14PS, whose page covers the bound, the special inputs and the Newton-Raphson step, and the AVX-512 successor of VRCPSS, which is bound only to 1.5 times 2^-12. The EVEX encoding adds a write mask on the one element and xmm16 to xmm31, and clears the register from bit 128 up. No MXCSR flag is ever set, and DAZ and FTZ apply. VRCP14SD is the double form.

Recorded on Zen 5#

• A small normal. 00F8CCFFh, near 2^-126, gave 7E03B600h, 0.89 times 2^-14 above the true reciprocal, with the last 9 significand bits zero.
• Denormals. Without DAZ the smallest denormal, 2^-149, gave +infinity, with no flag; under DAZ the largest gave +infinity too, as a zero. Under FTZ, 2^127 gave 0.
• An SNaN. With MXCSR 0, which unmasks every exception, 7F812345h came back as 7FC12345h, without a fault.
• Masked off. With bit 0 of K5 clear, the destination kept its low single and took bits 127:32 from the first source.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile 1.0f / x to VDIVSS, even with -ffast-math; adding -mrecip makes both use the older VRCPSS and a Newton-Raphson step, not VRCP14SS. The instruction comes from _mm_rcp14_ss(a, b) and its masked forms.

AMD’s Zen 5 latency spreadsheet gives one macro-op and 5 cycles, two per cycle on pipes FP1 and FP2.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f32[0] = rcp14(src3.f32[0])
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# rcp14: 1/a within 2^-14; Zen 5's 2
# recorded results: 0.8911 * 2^-14 at most
# denormals and tiny results by MXCSR.DAZ and FTZ; no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRCP14SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPTESTNMD
• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH

All 686 AVX10.1 instructions