VRCP28PD instruction (AVX512ER)

Forms

Every encoding of VRCP28PD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VRCP28PD zmm {k}{z}, zmm, {sae}` VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER	`EVEX.512.66.0F38.W1 CA /r`	AVX512ER
`VRCP28PD zmm {k}{z}, m512/m64bcst` VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER	`EVEX.512.66.0F38.W1 CA /r`	AVX512ER

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each double of the result comes from the double in the same place in each source.

Every double works alike: 8 doubles in the zmm form. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m64bcst, one double from memory stands for every element of the last source.

Result double i comes from double i of zmm2. Result doubles 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 0)[1] >> 27 & 1:
    fault(UD)                    # CPUID: no AVX512ER
for i in range(8):
    if k1[i]:
        zmm1.f64[i] = rcp28(src2.f64[i])
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# rcp28: 1/a within 2^-28, rounded to a double
# denormals are zeros and tiny results zeros, whatever MXCSR
# says; IE for an SNaN, ZE for a zero
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no AVX512ER, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VRCP28PD zmm {k}{z}, zmm/m512/m64bcst, {sae}`
`zmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`zmm/m512/m64bcst`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms: write masking; follows MXCSR
Memory forms: embedded broadcast (tuple Full); memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512ER_512` AVX512ER	AVX512ER `CPUID.(EAX=07H,ECX=0):EBX[27]` AVX512ER	Knights Landing, Knights Mill

VRCP28PD